Texas Instruments MSP50C6xx manual Deeper sleep …, Event Determined

Reduced Power Modes

either type of interrupt (internal or external). In most cases, the state of these bits should coincide.

The interrupt-trigger event associated with each of the two internal TIMERs is the underflow condition of the TIMER. In order for a TIMER underflow to occur during sleep, the TIMER must be left running before going to sleep. In certain cases, however, the act of going to sleep can bring a TIMER to stop, thereby preventing a TIMER-induced wake-up. The bottom row of Table 2–4 illustrates the various conditions under which the TIMER will continue to run after the IDLE instruction. Note that the reduced power mode DEEP leaves both TIMERs stopped after IDLE. This mode cannot, therefore, be used for a timed wake-up sequence.

Table 2–5. How to Wake Up from Reduced Power Modes (Refer to Table 2–3 and Table 2–4)

	→	deeper sleep …	relatively less power →
Event	Determined	LIGHT	MID	DEEP
	by Controls

Timer interrupts

TIMER1 and TIMER2	A, B, C
• Assuming respective IMR bit is set
• Assuming ARM bit is set as in C
External interrupts
Port F and D2,3,4,5 (if input)	C
• Assuming respective IMR bit is set
• Assuming ARM bit is set as in C
RESET	none
DAC Timer	D
• Assuming PDM bit is clear as in D

If TIMER is running,	No wake-up
	from TIMER.
then Underflow wakes device.

Rising-Edge, or Falling-Edge, as appropriate, wakes device.

RESET LOW-to-HIGH always wakes device.

No wake-up from DAC Timer.

The external interrupt is the other programmable option for waking the C6xx from sleep. The associated interrupt-trigger event is, in some cases, a rising- edge at the input port; in some cases it is a falling-edge. Refer to Section 3.1.5, Internal and External Interrupts, for a full description of these events. Consider also the comparator driven interrupts described in Section 3.3, Comparator. The input ports which are supported by external interrupt include the entire F Port, and, when programmed as inputs, Ports D2, D3, D4, and D5. Refer to Sec- tion 3.1, I/O, for a description of the various I/O configurations.

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