Instruction Classification

Table 4–20. Class 3 Instruction Description (Continued)

 

 

C3

 

 

Mnemonic

Description

 

 

 

 

 

 

 

0

1

0

0

0

XOR An[~], An~, An [, next A]

Logically exclusive OR accumulator with offset

 

 

 

 

 

XORS An[~], An~, An

accumulator and store the results in accumulator (~A=0 or

 

 

 

 

 

 

1). ALU status is modified.

 

 

 

 

 

 

 

0

1

0

0

1

OR An[~], An~, An [, next A]

Logically OR accumulator with offset accumulator and

 

 

 

 

 

ORS An[~], An~, An

store results into accumulator (~A=0 or 1). ALU status is

 

 

 

 

 

 

modified.

 

 

 

 

 

 

 

0

1

0

1

0

AND An[~], An~, An [, next A]

Logically AND accumulator with offset accumulator and

 

 

 

 

 

ANDS An[~], An~, An

store result(s) into accumulator (~A=0 or 1). ALU status is

 

 

 

 

 

 

modified.

 

 

 

 

 

 

 

0

1

0

1

1

SHRAC An[~], An[~] [, next A]

Shift accumulator or offset accumulator right 1 bit and

 

 

 

 

 

SHRACS An[~], An[~]

store result in accumulator (~A=0 or 1). MSB will be set to

 

 

 

 

 

 

zero or be set equal to the sign bit (XSGM dependent).

 

 

 

 

 

 

ALU status is modified.

 

 

 

 

 

 

 

0

1

1

0

0

SUB An[~], An[~], PH [, next A]

Subtract product high register from accumulator (A~=0) or

 

 

 

 

 

SUBS An[~], An[~], PH

from offset accumulator (A~=1) and store the result into

 

 

 

 

 

accumulator (~A=0) or into the offset accumulator (~A=1).

 

 

 

 

 

 

ALU status is modified. String bit causes subtract with

 

 

 

 

 

 

carry status (CF).

 

 

 

 

 

 

 

0

1

1

0

1

ADD An[~], An[~], PH [, next A]

Add product high register to accumulator or to offset

 

 

 

 

 

ADDS An[~], An[~], PH

accumulator and store the result into accumulator (~A=0

 

 

 

 

 

or 1). ALU status is modified. The string bit causes an add

 

 

 

 

 

 

with carry status (CF).

 

 

 

 

 

 

 

0

1

1

1

0

MOV An[~], PH [, next A]

Transfer product high register to accumulator (~A=0) or

 

 

 

 

 

MOVS An[~], PH

offset accumulator (~A=1). ALU status is modified. String

 

 

 

 

 

bit will cause stringing with current ZF status bit.

 

 

 

 

 

 

 

0

1

1

1

1

EXTSGN An[~] [, next A]

Copy SF bit in status register to all 16 bits of the

 

 

 

 

 

EXTSGNS An[~]

accumulator or offset accumulator. On strings, the

 

 

 

 

 

accumulator address is preincremented causing the sign

 

 

 

 

 

 

of the addressed accumulator to be extended into the next

 

 

 

 

 

 

accumulator address.

 

 

 

 

 

 

 

1

0

0

0

0

CMP An~, An [, next A]

Subtract offset accumulator from accumulator(A~=0) or

 

 

 

 

 

CMP An, An~ [, next A]

subtract accumulator from offset accumulator (A~=1) and

 

 

 

 

 

CMPS An~, An

store the status of the result into ALU status. Accumulator

 

 

 

 

 

CMPS An, An~

or offset accumulator original value remains unchanged.

 

 

 

 

 

 

 

1

0

0

0

1

reserved

N/A

 

 

 

 

 

 

 

1

0

0

1

0

reserved

N/A

 

 

 

 

 

 

 

1

0

0

1

1

reserved

N/A

 

 

 

 

 

 

 

These instructions have a special 1 word string operations when string mode is selected. The instructions ignore the string count, executing only once, but maintain the carry and comparison to zero operation of the previous arithmetic operation as if the sequence of the previous string instruction and current instruction were part of a larger string operation.

4-32

Page 118
Image 118
Texas Instruments MSP50C6xx Zero or be set equal to the sign bit Xsgm dependent, SUB a n~, a n~, PH , next a, Reserved