Texas Instruments MSP50C6xx manual Hardware Initialization States

Hardware Initialization States

3.5 Hardware Initialization States

The RESET pin is configured at all times as an external interrupt. It provides for a hardware initialization of the MSP50C6xx. When the RESET pin is held low, the device assumes a deep sleep state and various control registers are initialized. After the RESET pin is taken high, the Program Counter is loaded with the value stored in the RESET Interrupt Vector.

Note: Internal Power Reset Function

There is no power-on reset function internal to the MSP50C6xx. After the ini- tial power-up or after an interruption in power, the RESET pin must be cycled low-to-high. The application circuitry must therefore provide a mechanism for accomplishing this during a power-up transition or after a power fluctua- tion.

The application circuits shown in Section 6.1, Application Circuits, illustrate one implementation of a reset-on-power-up circuit. The circuit consists of an RC network (100 kΩ , 1 ∝ F). When powering VDD from 0 V, the circuit provides some delay on the RESET pin’s low-to-high transition. This delay helps to en- sure that the MSP50C6xx initialization occurs after the power supply has had time to stabilize between VDD MIN and VDD MAX. VDD MIN and VDD MAX are the minimum and maximum supply voltages as rated for the device. The circuit shown, however, may not shield the RESET pin from every kind of rapid fluc- tuation in the power supply. At any time that the power supply falls below VDD MIN, even momentarily, then the RESET pin must be held low and then high once again, either by the user of the device or by some other external circuitry (refer to the MSP50C6xx data sheet (SPSS023), Electrical Specifications sec- tion).

When the RESET pin is held low, the MSP50C6xx is considered reset and has the following internal states:

RESET low . . .

I/O ports are be placed in a high impedance Input condition: Ports A, B,

C, D, and E.

All outputs on Port G is are set to low (0x0000).

Device is placed in a deep sleep state.

PLL circuitry, master clock, CPU clock, and TIMERs are stopped.

Current draw from the VDD is less than 10 ∝ A in this condition.

-Interrupt flag register (IFR at address 0x39) is not automatically cleared. Internal RAM is not automatically cleared.

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