Texas Instruments MSP50C6xx manual = the value programmed at TM5 … TM0 true, Protection marker

Memory Organization: RAM and ROM

[(NTM + 1) * 512 – 1] = highest ROM address within the block to be

	protected
(NTM + 1) * 512	= lowest ROM address which is left unprotected
NTM	= the value programmed at TM5… TM0 (true
	protection marker)
NFM	≡ the binary complement of NTM
NFM	= the value programmed at FM5… FM0 (false
	protection marker)

The purpose of the true and false protection markers is to provide parity. An erased P614 EPROM cell defaults to the value 1. Once programmed from 1 to 0, it cannot be programmed back to 1, unless the cell (and all other cells along with it) are subject to erasure. A multi-pass programming, therefore, can only lower the value stored at an EPROM address and never raise it. Once a valid block-partition address has been properly specified in both TM and FM, it is impossible to change TM to another address and still maintain parity with FM.

Note: Block Protection Mode

When applying the block protection mode, bits FM5 through FM0 must be programmed as the logical inverse of bits TM5 through TM0, respectively.

Across the span of the 32k word ROM space, there are 64 possible values for NTM (including zero). Hence, the 6-bit-wide locations for TM and FM.

The two single-bit fields found within the block protection word are the block protection bit (BP) and the global protection bit (GP). If BP and GP are both SET (erased), then no protection is applied to the ROM.

If BP is CLEAR and GP is SET, then the block protection mode is engaged. This means that read and write access is prevented at locations 0x0000 through [(NTM + 1) ⋅ 512 – 1]. Read and write access is permitted at locations [(NTM + 1) ⋅ 512] through 0x7FFF.

If GP is CLEAR, then the global protection mode is engaged. This prevents read and write access to all addresses of the ROM, regardless of the value of BP.

Note: Block Protection Word

The remaining bits in the block protection word are reserved for future use, but must remain set in order to ensure future compatibility. These bits are numbers 6, 15, and 16.

MSP50C6xx Architecture 2-21