Interrupt/General Control Register | Texas Instruments MSP50C6xx

Interrupt/General Control Register

3.4 Interrupt/General Control Register

The interrupt/general control (IntGenCtrl) is a 16-bit wide port-mapped register located at address 0x38. The primary component in the IntGenCtrl is the 8-bit interrupt mask register (IMR). The IMR is used to individually enable all interrupts except RESET. Each bit of the IMR is associated with one of the interrupts described in Section 3.1.5. An interrupt is enabled when the appropriate IMR bit is set. The IMR is located at bits 0 through 7 in the IntGenCtrl. Bit 0 is associated with INT0, which is the highest priority interrupt. Bit 7 is associated with INT7. Refer to Section 2.7, Interrupt Logic, for more information regarding the interrupt-system logic and initialization sequence.

IntGenCtrl register

address 0x38

(16-bit wide location)

15

14

13

12

11

10

09

08

07

06

05

04

03

02

01

00

CE

AR

PD

EP

E2

E1

S2

S1

D5

D4

PF

D3

D2

T2

T1

DA

low

high

priority

priority

0x0000 : State after RESET low

Interrupt mask register

CE : Comparator enable

D5

: port D5 falling-edge

AR : ARM bit

D4

: port D4 rising-edge

PD : Pulse-density clock: PDMCD

PF

: any port F falling-edge

EP : Enable pullup resistors on port F

D3

: port D3 falling-edge

E2

: Enable TIMER2 (1 value starts timer)

D2

: port D2 rising-edge

E1

: Enable TIMER 1 (1 value starts timer)

T2 : TIMER2 underflow

S2

: Clock source for TIMER2 (0 = MC/2, 1 = ref Osc)

T1 : TIMER1 underflow

S1

: Clock source for TIMER1 (0 = MC/2, 1 = ref Osc)

DA : DAC timer underflow

(1 value enables interrupt service)

The remaining bits in the IntGenCtrl have various control functions which are not directly related to the interrupt system. Four of these are related to the timer functions. Bits 8 and 9 are used to select the clock sources which govern the rates of TIMER1 and TIMER2. Clearing bit 8 chooses 1/2 MC as the source for TIMER1 (i.e., the TIMER runs at one-half the frequency of the Master Clock). Setting bit 8 chooses the reference oscillator (RTO or CRO) as the source for TIMER1. (The same applies for bit 9 and TIMER2.) Bits 10 and 11 are used to enable TIMER1 and TIMER2, respectively. Setting bit 10 starts TIMER1, and clearing bit 10 stops TIMER1. (The same applies for bit 11 and TIMER2).

3-18

Image 82

Texas Instruments MSP50C6xx manual Interrupt/General Control Register, IntGenCtrl register, Address Bit wide location Low

Contents

MSP50C6xx Mixed-Signal Processor User’s Guide Important Notice Notational Conventions How to Use This ManualAbout This Manual Iii Csr -a /user/ti/simuboard/utilities Here is a sample program listingNotational Conventions This book may contain cautions and warnings Information About Cautions and WarningsTrademarks Information About Cautions and WarningsPage Contents Contents Assembly Language InstructionsPeripheral Functions Contentsix Code Development Tools Applications Customer Information Contentsxi PLL Performance -27 2-10 Instruction Execution and Timing Tables Contentsxiii Tables Xiv Introduction to the MSP50C6xx Features of the MSP50C6xx Features of the MSP50C6xx Industrial ApplicationsConsumer Education Aids for the Handicapped Development Device MSP50P614 Development Device MSP50P614 Functional Description for the MSP50C614 Functional Description for the MSP50C614 Functional Description for the MSP50C614 Crystal Reference Oscillator Connections Resistor Trim Oscillator Connections Reset Circuit MSP50C601, MSP50C604, and MSP50C605 MSP50C601, MSP50C604, and MSP50C605Page MSP50C6xx Architecture Architecture Overview MSP50C6xx Core Processor Block Diagram MSP50C6xx Architecture Computational Unit Block Diagram Signed and Unsigned Integer Representation Computation UnitMultiplier Computation Unit Computation Unit Overview of the Multiplier Unit Operation Arithmetic Logic Unit Accumulator Block Overview of the Arithmetic Logic Unit Points to AC Register #Points to Offset Data Memory Address Unit Data Memory Address Unit RAM Configuration Data Memory Address Unit Data Memory Addressing Modes Bit Logic Unit Program Counter UnitProgram Counter Unit Memory Map Memory Organization RAM and ROMMemory Organization RAM and ROM C6xx Memory Map not drawn to scale Peripheral Communications Ports Reset LOW Summary of MSP50C614’s Peripheral Communications Ports Interrupt Vectors Summary of C614’s Peripheral Communications PortsInterrupt Name ROM address Event Source Interrupt Priority ROM Code Security Write only Block Protection WordAddress 0x7FFE True Protection Marker N TM ≡ the binary complement of N TM = the value programmed at TM5 … TM0 trueProtection marker = the value programmed at FM5 … FM0 false Macro Call Vectors Interrupt LogicInterrupt Logic Bit wide location 00 ← INT number IFR Interrupt Logic Interrupt Initialization Sequence PLL Performance Clock ControlOscillator Options Clock Control PLL Performance Clock Speed Control Register Clock frequency kHz = Pllm register value + 1 ⋅ 65.536 kHz RTO Oscillator Trim Adjustment ClkSpdCtrl register Rtrim Register Read Only Applies to MSP50C6xx Device Only ClkSpdCtrl Value Copied Shaded Timer Registers Timer Registers Timer Registers Reduced Power Modes Reduced Power Modes Reduced Power Modes Reduced Power Modes Programmable Bits Needed to Control Reduced Power Modes Component Determined Deeper sleep … relatively less power →By Controls Deeper sleep … Event Determined Global interrupt enable is SET Execution Timing Execution Timing Peripheral Functions MSP50C614 I/OGeneral-Purpose I/O Ports MSP50C604 MSP50C605 0x14h 0x1Ch 0x24h Possible control values = High-Z Input Control register address 0x04h†Peripheral Functions Dedicated Input Port F Input Port F Dedicated Output Port GData register address Branch on D Port Totem-Pole Output Port G Internal and External Interrupts Summary of the interrupts is given in Table InterruptsInterrupt Vector Source Trigger Event Priority Comment DAC Control and Data Registers Digital-to-Analog Converter DACPulse-Density Modulation Rate Digital-to-Analog Converter DAC Overflow bits Least-significant data value Ignored bits PDM Clock Divider PDM Clock Divider Digital-to-Analog Converter DAC Example 3-1 -kHz Sampling Rate DAC Example 3-2 -kHz Sampling Rate Comparator INT6 INT7 TIMER1 Enable Comparator IntGenCtrl register Interrupt/General Control RegisterInterrupt/General Control Register Address Bit wide location Low Interrupt/General Control Register Hardware Initialization States Hardware Initialization States Hardware Initialization States Bit Bit Name Initialized Value Description Assembly Language Instructions Instruction Set Summary Introduction System Registers System Registers Assembly Language InstructionsTop of Stack, TOS Postdecrement Product Low Register PL Product High Register PHAccumulators AC0-AC31 Bit Accumulator Pointers AP0-AP3Indirect Register R0-R7 Bits 16 String Register STR Status Register Stat Status Register Stat Function Instruction Syntax and Addressing Modes 1 MSP50P614/MSP50C614 Instruction Syntax Bit Opcode Addressing Mode EncodingAddressing Modes Next a Addressing Mode Bits and adrs Field Description Rx Bit Description MSP50P614/MSP50C614 Addressing Modes Summary Auto Increment and Auto Decrement Modes Flagadrs Flag addressing mode encoding, flagadrsFlag Repeat Clocks Words Addressing Operation, † Syntax Example Immediate AddressingSyntax ADD AP0, 0x1A Mulr *0x02A1 Direct AddressingMOV *0x012F * 2, *A0 Memory Operand SyntaxOperation Indirect AddressingIndirect Addressing Syntax Rx x = 0 Address Memory Operand ++  --  ++R5 *R4++ Relative AddressingMOV A2, *R0 Movb *R7++, A3 Rx x = 0 Address Index Register R5 Operand A0, *R3+R5R6 page register Address Bit positive offset Operand MOV A3, *R6+0x10 Rx x = 0 Address Memory Operand Or TF2, *R6+0x02 Flag AddressingTF1, *0x20 XOR TF1, *R6+0x20 8 Tag/Flag Bits Possible sources of confusion Consider the following code TF1,*ram1 TF1 bit in Stat is set!? Instruction Classification 10. Symbols and ExplanationSymbol Explanation Instruction Classification Next a Accumulator control bits as described in Table 11. Symbols and Explanation11. Instruction Classification Class Sub- Description Class Sub Description 12. Classes and Opcode Definition Class 1 Instructions Memory and Accumulator Reference C1a ~A~ 13. Class 1 Instruction Encoding14. Class 1a Instruction Description C1b 15. Class 1b Instruction Description C1b Mnemonic Description Class 2 Instructions Accumulator and Constant Reference 17. Class 2a Instruction Description 16. Class 2 Instruction EncodingC2a Mnemonic Description C2b Mnemonic Description 18. Class 2b Instruction DescriptionClass 3 Instruction Accumulator Reference ADD An ~, An ~, imm16 , next a Mnemonic Description 19. Class 3 Instruction Encoding20. Class 3 Instruction Description Subs An~, An~, An Modified ADD An~, An~, An , next a ALU status is modified. String bit causes subtract with Zero or be set equal to the sign bit Xsgm dependentSUB a n~, a n~, PH , next a Carry status CF Is modified PH msbs extended by XM mode bit. Transfer the lowerMOV SV, An~ , next a From the offset accumulator A~=1 or accumulator Class 4 Instructions Address Register and Memory Reference 21. Class 4a Instruction Encoding 24. Class 4c Instruction Description 22. Class 4a Instruction Description23. Class 4b Instruction Description 25. Class 4d Instruction Description 27. Class 5 Instruction Description Class 5 Instructions Memory Reference26. Class 5 Instruction Encoding Adrs. Transfer status is modified Stag adrs Dressing mode adrs. Transfer status is modifiedMOV adrs, TOS Tag bit 29. Class 6a Instruction Description Class 6 Instructions Port and Memory Reference28. Class 6a Instruction Encoding C6a Mnemonic Description Class 7 Instructions Program Control 30. Class 6b Instruction DescriptionC6b Mnemonic Description Jcc 31. Class 7 Instruction Encoding and DescriptionVector8 Ccc Class 8 Instructions Logic and Bit 32. Class 8a Instruction Encoding Class 9 Instructions Miscellaneous 33. Class 8a Instruction Description34. Class 8b Instruction Description C8a Mnemonic Description 37. Class 9b Instruction Description 35. Class 9a Instruction Encoding36. Class 9a Instruction Description C9a Mnemonic Description 39. Class 9d Instruction Description Bit, Byte, Word and String Addressing38. Class 9c Instruction Description C9c Mnemonic Description Word Global Flags Relative0000h 0001h 0002h 0040h 0041h Nnnn 17th Bit 0000h MS Byte LS Byte Movb A0, *0x0003 Mode Address Used Data Order Rx Post modify †40. Data Memory Address and Data Relationship MOV A0, *0x0004 Which uses the absolute word memory address Rflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational Modes Computational Setting Resetting Function Mode Instruction 41. MSP50P614/MSP50C614 Computational Modes SXM Example 4.6.2 Sovm Example 4.6.1 SovmExample 4.6.1 SXM Hardware Loop Instructions Hardware Loop Instructions Syntax Operation Limitations 42. Hardware Loops in MSP50P614/MSP50C614Completion of the BEGLOOP/ENDLOOP block Data memory *address = data String Instructions43. Initial Processor State for String Instructions Program memory *address = data Mulapl A0, A0~ Lookup Instructions Lookup Instructions44. Lookup Instructions Instructions Description Data Transfer MOV An, adrs SUB An MOV An, *An Input/Output Instructions Input/Output InstructionsSpecial Filter Instructions Xk-2 Xk+2 Xk-1 xk+1 32 or Special Filter Instructions Special Filter Instructions STR,0 0x0106 0x0100 0x01020x0104 Go back N words to wrap around After FIR/COR execution Important Note About Setting the Stat Register Firkcoeffs FIR/COR only = 0..N Coeffarray address FIRK/CORK only Program memory FIRK/CORKCoeffarray Samplebuf address Coeffarray Samplebuf Coeffarray is stored Conditionals Conditionals Offset16 ≤ Symbol MeaningOperands Port4 ≤ Port6 ≤ Dma n AdrsnClk Flg Pma n Offset nPort n 45. Auto Increment and Decrement 46. Addressing Mode Bits and adrs Field Description47. Flag Addressing Syntax and BIts Individual Instruction Descriptions Individual Instruction Descriptions 14.1 ADD Add word Execution Description See Also PC PC + Flags Affected AddbOpcode Adds Add String Clock , clk Words , w Adds A1, A1~, A1 14.4 Bitwise A3, *R4 ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XorsTF2, *0x0020 OF, SF, ZF, CF are set accordingly Andb Bitwise and ByteSrc byte PC PC + Clock , clk Word , w Ands A0, A0~, A0 Ands Bitwise and StringAnds A0, A0~, *R2 Flags Affected None Opcode Begloop Begin LoopSave next instruction address PC + Order to loop N times Call Unconditional Subroutine Call RET TOS 14.9 CccNOP 48. Names for cc True condition Not true condition Syntax Alternate Syntax Description CTF1 CALL, VCALL, RET, Iret0x2010 Crnbe PC = PC + w 14.10 CMP Compare Two WordsStat flags set by src src1 operation CMPB, CMPS, Jcc, Ccc CMP R2, 0xfe20 CMP R0, R5 Cmpb Compare Two Bytes Cmpb R3 Cmps A1~ Cmps Compare Two StringsPC PC + w Flags Affected Cmps A2, A2~ An, *Rx 3nR+2 With RPT instruction. See .11 for more detail on the setup14.13 COR Correlation Filter Function Rxeven = Rxeven + R5 3n R+2 Cork Correlation Filter FunctionSample data. During Cork execution, interrupt is queued Xeven = R xeven + R5 Argument, it assumes n =1 Endloop End LoopDecrement R4 by n 1 or PC first address after Begloop else BEGLOOP, Inte Copy accumulator sign flag SF to all 16 bits of a n ~ Extsgn Sign Extend Word~ , next a Dest , mod Extsgns Sign Extend String An~ 100 An, *Rx 2nR+2 Assembly Language Instructions 10114.18 FIR FIR Filter Function Coefficients in RAM Rxeven++ 102 Assembly Language Instructions 103 Firk Idle Halt Processor 104 INS, OUT, Outs 14.21 Input From Port Into WordA2~, 0x3d 14.22 INS Input From Port Into String IN, OUT, Outs STAT.IM Intd Interrupt DisableAssembly Language Instructions 107 IM is Stat bit PC PC + Flags Affected None Opcode INTD, Iret Interrupt EnableInte Clock, clk Word, w With RPT, clk Class Assembly Language Instructions 109 Iret Return From Interrupt Conditional Jumps RCF and RZF affected by post-modification of R Assembly Language Instructions 111 Cc names If test condition is false, a NOP is executed JE 0x2010, R3++R5 See Also JMP, CALL, C cc ExampleJNZ Jtag 0x2010, R2++ See Also Cc, CALL, C cc Example 14.27 JMP Unconditional JumpPost-modify R x if specified Instruction Operation 14.28 MOV Move Data Word From Source to Destination TF n, cc , R XSF, XZF are set accordinglyClock , clk Word , w With RPT , clk Class STR, imm8 Assembly Language Instructions 117 MOV adrs, DP With some operand types Example 4.14.28.11 MOV A1~, *A1 MOVU, MOVT, MOVB, MOVBS, MovsExample 4.14.28.10 MOV MR, A3, --A Example 4.14.28.12 MOV *0x0200 * 2, R0 Transfer R5 to R0 Example Example 4.14.28.13 MOV R1, 0x0200Example 4.14.28.15 MOV *0x0200 * 2, R0 Example 4.14.28.18 MOV *R6 + 8 * 2, DP Execution An + PH Movaph Move With Adding PHMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs Background. See .8 for more details Movaphs Move With Adding PHExecution + PH MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs Movb A0, *R2 Movb Move Byte From Source to DestinationCopy value of unsigned src byte to dest byte Copy data memory byte pointed by R2 to accumulator A0 Movb A0, 0xf2 Movb *R2, A0Movb R2 Movbs A2, *0x0200 Movbs Move Byte String from Source to DestinationTAG bit is set to bit 17th value Movbs *0x0200, A2 Adrs , An ~ Movs Move String from Source to DestinationAn ~ , adrs Adrs , *An Movs A1, A1~ MOVU, MOV, MOVT, MOVB, MovbsMovs A2~ Movs A1~, A1 MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs Movsph128 Movsphs Move String With Subtract From PH An second word PH MR contents of adrsAssembly Language Instructions 129 Details Available MovtPC PC + w Flags Affected None Opcode MOVU, MOV, MOVT, MOVB, MOVBS, Movs MOV, MOVB, MOVT, MOVBS, Movs Movu Move Data UnsignedTAG bit is set accordingly UM is set to Copy the value pointed by R3 to MR Xxxxxx Xxxx00 Flag Bit MR/SV An S APn132 Accumulator pointer if specified 14.38 MUL Multiply RoundedMR * src PC PC + w Flags Affected MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl MULS, MUL, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls Mulr Multiply Rounded With No Data TransferMR * src PC PC + Flags Affected Mulapl Muls Multiply String With No Data Transfer Length nS+2, where nS is the value in STR registerAssembly Language Instructions 135 PH,PL MR * src string Background. See .8 for more detail Mulapl Multiply and Accumulate ResultPH ,PL MR * src MULAPLS, MULSPL, MULSPLS, MULTPL, Multpls MR * src Mulapls Multiply String and Accumulate ResultMULAPL, MULSPL, MULSPLS, MULTPL, Multpls MULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls Mulspl Multiply and Subtract PL From AccumulatorOccuring in the background. See .8 for more details Syntax Description Mulspl adrs MULSPL, MULTPL, MULTPLS, MULAPL, Mulapls Mulspls Multiply String and Subtract PL From AccumulatorFrom dest string Syntax Description Mulspls adrs Value of src. The 16 MSBs Multpl Multiply and Transfer PL to Accumulator~ , a n ~ , next a Multiply MR by data memory word, move PL to a n MULTPL, MULAPL, MULAPLS, MULSPL, Mulspls MultplsExecution PH, PL MR * src PC PC + Flags Affected Example 4.14.46.2 Multpls A2, A2~ NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Negac Two’s Complement Negation of AccumulatorAccumulator Example 4.14.47.1 Negac A3~, A3, --A Dest accumulator string Assembly Language Instructions 143Negacs Two’s Complement Negation of Accumulator String NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Execution PC PC + 14.49 NOP No OperationRPT NEGAC, Negacs Notac One’s Complement Negation of AccumulatorNOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors Example 4.14.50.1 Notac A3~, A3, --A Negacs Notacs One’s Complement Negation of Accumulator StringAccumulator string A3~ TFn bits in Stat register are set accordingly 14.52 or Bitwise Logical orAccumulator pointers are allowed with some operand types Or TF1, *R6+0x22 ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOr A0, *R0++R5 148 Accumulator is affected 14.53 ORB Bitwise or ByteOr src OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs OR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs 14.54 ORS Bitwise or StringPC + w Flags Affected ORS A0, A0~, A0 Address is multipled by 4 to get the actual port address 14.55 OUTOUTS, IN, INS OUT, IN, INS Outs Output String to PortPort6 specified in the instruction Port6 , An ~ R7 R7 Flags Affected 14.57 RET Return From Subroutine CALL, CccPC TOS CALL, i.e., RET followed by a RET should not be allowed Sflag , Stag , Rtag Rflag Reset Memory FlagExample 4.14.58.2 Rflag *R6 + 14.59 RFM Reset Fractional Mode SyntaxResets the fractional mode. Clears FM bit of Stat STAT.FM Resets the overflow mode to zero Rovm Reset Overflow ModeSaturation output normal mode Stat .OM Load imm8 to repeat counter 14.61 RPT Repeat Next InstructionIf RPT adrs8 Load src to repeat counter After execution completes Rtag *R6+0x0002 Rtag Reset TagStag , Rflag , Sflag Rtag *R6+0x0003 STAT.XM 14.63 RXM Reset Extended Sign ModeAssembly Language Instructions 159 SXM Rflag , Stag , Rtag Address flagadrs only accesses the 17 th bitSflag Set Memory Flag 160 Assembly Language Instructions 161 14.65 SFM Set Fractional ModeMode for signed fractional arithmetic Set fractional mode. Set FM bit of Stat to Accumulator. Use Shlac for this purpose 14.66 SHL Shift LeftPH , PL Shls Shift accumulator A1 by one bit to the left Shlac Shift Left AccumulatorIts offset. LSB of result is set to zero Example 4.14.67.2 Shlac A1~, A1, --A Accumulators in the string Shlacs Shift Left Accumulator String Individually164 Shlapl A2, *R1++ Shlapl Shift Left with AccumulateExample 4.14.69.1 Shlapl A0, *R4++R5 Example 4.14.69.3 Shlapl A1, A1, ++A Shift data memory string left, add PL to a n Shlapls Shift Left String With AccumulateShift a n ~ string left, addb PL to a n ~ Execution PH, PL Assembly Language Instructions 167Shls Shift Left Accumulator String to Product An~ Shlspl A2, *R1++ Shlspl Shift Left With Subtract PLExample 4.14.72.1 Shlspl A0, *R4++R5 Example 4.14.72.3 Shlspl A1, A1, ++A NS+3 NR+3 Assembly Language Instructions 169Shlspls Shift Left String With Subtract PL Shift RAM string left, subtract PL from An Shltpl A2, *R1++ Shltpl Shift Left and Transfer PL to AccumulatorExample 4.14.74.1 Shltpl A0, *R4++R5 Example 4.14.74.3 Shltpl A1, A1, ++A SHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls Shltpls Shift Left String and Transfer PL to AccumulatorReceives the same data as PH Shift the accumulator string A1 by nSV bits to the left Shift right one bit the accumulator A1 Shrac Shift Accumulator RightRegister Example 4.14.76.2 Shrac A1~, A1, ++A SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl Assembly Language Instructions 173Shracs Shift Accumulator String Right Shltpls Sovm Set Overflow Mode SyntaxOutput DSP mode STAT.OM RTAG, RFLAG, Sflag StagStag *0x401 An ~ , An , adrs , next a 14.80 SUB SubtractDest, src , src1 , next a An ~ , An ~ , imm16 , next a SUB A3~, A3, *R4 Example 4.14.80.2 SUB A0, A0, 2, ++ASUB A1, A1~, A1 SUB R3, R5 Subtract 0xF2 from register R3 byte Subb Subtract ByteSubtract 0x45 from accumulator A2 byte Syntax Description Subb a n, imm8 Subs Subtract Accumulataor String Assembly Language Instructions 179NR+2 Subs A3~, A3~, PH Subs A2, A2, A2~Subs A2, A2~, A2 180 Assembly Language Instructions 181 14.83 SXM Set Extended Sign ModeSets extended sign mode status register Stat bit 0 to RXM R7 R7 + Flags Affected Vcall Vectored CallPush PC + 0x7F00 See Also RET, IRET, CALL, C cc Example XOR src For three operands 14.85 XOR Logical XORXOR src For two operands TAG bit is set accordingly Src is flagadrs Example 4.14.85.1 XOR A1, A1, 0x13FF XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsExample 4.14.85.2 XOR A0, A0, 2, ++A Xorb Logical XOR Byte Assembly Language Instructions 185XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors Logical XOR StringDest string Xors A2, A2~, A2 Zacs 14.88 ZAC Zero AccumulatorPC PC + Flags Affected ZF = ZAC A1~, ++A Zero the specified accumulator string Reset the content of offset accumulator string A1~ to zeroZacs Zero Accumulator String ZAC Instruction Set Encoding Assembly Language Instructions 189Instruction Set Encoding 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 Assembly Language Instructions 195 196 Assembly Language Instructions 197 Description True condition Not true condition Instruction Set Summary An~, pma16 Pma16 , Rmod Assembly Language Instructions 199An~, An~ , next a An, An~ An ~, imm16 , next a Adrs, a n~ , next a~, adrs , next a MR , imm16 , next a STR, adrs Assembly Language Instructions 201Adrs, TOS Flagadrs† , TFn ~ , a n~ ~ , next a~, a n~ , next a Adrs An ~, An ~, imm16 , next a ~, a n~, a n , next a An~, An~, pma16 An~, An~ , next a NR+3 Assembly Language Instructions 203TFn, flagadrs NR+3 TFn, cc , Rx An~, An~, An ~, a n, a n~ ~, a n~~, a n, a n~ , next a ~, a n~, PH Conditional on RZF=1 Not condition RZF=0 Conditional on RCF=1 Not condition RCF=0Conditional on RZF=0 and RCF=1 Not condition RZF≠ 0 or RCF≠ Conditional on ZF=0 and SF=1 Not condition ZF≠ Or SF≠ 206Assembly Language Instructions Instruction Set Summay MC = Pllm value+1 ⋅ 131.07 kHz 208Assembly Language Instructions 209 Language InstructionsSummay Instruction Set Summay 210Assembly Language Instructions Code Development Tools Introduction Pin IDC Connector top view looking at the board Code Development Tools SDK50P614 kit of 15 MSP50P614s MSP50C6xx Development Tools GuidelinesCategories of MSP50Cxx Development Tools MSP50C6xx Development Tools Guidelines Tools Definitions SPEECH-EVM†PC50C604† MSP50C6xx Development Tools Guidelines Software Tools-Definitions Documentation MSP50C6xx Code Development ToolsSystem Requirements Hardware Tools Setup Red MSPSCANPORTI/F power Yellow Green Target board power Examples AssemblerAssembler Directives Assembler An assembly language program #ELSE see #IF and #IFDEF Do other things here #IF expression Do something here#ELSE #ENDIF Example #IFDEF symbol #IFNDEF symbol Assembler Foreword CompilerCompiler External References Variable TypesType Name Mnemonic Range Size in Bytes Example Without Arguments Defines a replacement string for a given stringDirectives With Arguments Include Files See #if directive #define STRLENGTHi Major Differences between C and C RAM Usage Function Prototypes and DeclarationsInitializations Initialization values are stored in program memory String Functions String FunctionsOperator can take the following values predefined constants Constant Functions An example of the use of xferconst is This section is C- specific Implementation DetailsComparisons Signed comparison of a and b. a is in A0, b is in A0~ Ult Assembly VectorUnsigned comparison of a and b. a is in A0, b is in A0~ Ugt Stack frame has the following structure DivisionFunction Calls Low Address High Address On Call Programming ExampleCmmfunc bidonint i1,char *i2 is valid, but On RET #include cmmmacr.h Programming Example, C -- With Assembly Routines Reserved Implementation Details R7Param Addb R7,2 To C function return in roncoreturn OldR5 Return Addr Param R7,R5 Stack data Param R7,R5 Stack data Before call Parameter Return Addr Param Stack data To ASM function return EfficiencyEfficiency Efficiency Real Time Clock Example Example 5-1. First Project Jrtc.rpj Hmodules Allocated by changing MAINRAM.IRX Efficiency CMM1.ASM Sixth file, cmm1ram.asm, allocates memory for cmm1.asm Allocated as follows MAIN.CMM Example 5-2. Second Project C-- With Speech Dspvar.irx dsputil.asm getbits.asm speak.asm speak.irx Celp Celp.irxUtil.obj Isr Tim2isr.asm dacisr.asm J tim1isr.asm Ampm.qfm Tens.qfmMelp Dsp Ramendcustomer Ramstartcustomer New C-- callable functions were declared global Assembly routines that will be called are declared externalClock will need to say Cmmfunc speakHours Example 5-3. Third Project C-- with an LCD Lcd Lcd.asm Lcd.irx Melp.irx Melp.objCelp Ampm.qfm Days.qfm Ones.qfm Teens.qfm External lcdsetio external lcdinit Case Efficiency Beware of Stack Corruption Beware of Stack Corruption Reported Bugs With Code Development Tool Reported Bugs With Code Development Tool Applications Application Circuits Application Circuits 3300 pF ∝ F 22 pFMSP50P614 only 100 kΩ Applications6-3 Initializing the MSP50C6xx Initializing the MSP50C6xx File init.asm Applications6-5 JNZ Itsacpart Itsappart Applications6-7 Getting Started TI-TALKS Example CodeTI-TALKS Example Code RAM Overlay RAM OverlayCreating a New Project Applications6-9 RAM Overlay Adding Customer Variables Common Problems Page Customer Information Die Bond-Out Coordinates Mechanical InformationPackage Information Signal and Pad Descriptions for the MSP50C614 Customer Information Signal and Pad Descriptions for the MSP50C605 Signal and Pad Descriptions for the MSP50C601 Signal and Pad Descriptions for the MSP50C604 Pin QFP Mechanical Information 13 NOM 13 12 11 10 9 8 7 6 5 4 3 2 Extra pin 3 4 5 6 7 8 9 10 11 12 13 Bottom View Bottom View of 120-Pin PGA Package of the MSP50P614 Bottom view Customer Information Fields in the ROM Customer Information Fields in the ROM0x0006 Device number 0x0614 Device Production Sequence Speech SpecificationSpeech Development Cycle Software Design Hardware Design Device Production Sequence 6xx Ordering InformationNew Product Release Forms Nprf Code Letter PJM Loopin 100-Pin QFP New Product Release Forms Nprf Approval of Prototypes and Authorization to Start Production NEW Product Release Form for MSP50C604 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C605 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C601 Option Selection New Product Release Forms Nprf Additional Information Topic Additional Information Additional Information