MSP50C6xx Mixed-Signal Processor User’s Guide
Important Notice
Notational Conventions
How to Use This Manual
About This Manual
Iii
Notational Conventions
Here is a sample program listing
Csr -a /user/ti/simuboard/utilities
This book may contain cautions and warnings
Information About Cautions and Warnings
Trademarks
Information About Cautions and Warnings
Page
Contents
Peripheral Functions
Assembly Language Instructions
Contents
Contentsix
Code Development Tools
Applications
Customer Information
Contentsxi
PLL Performance -27 2-10 Instruction Execution and Timing
Tables
Contentsxiii
Tables
Xiv
Introduction to the MSP50C6xx
Features of the MSP50C6xx
Features of the MSP50C6xx
Industrial
Applications
Consumer Education
Aids for the Handicapped
Development Device MSP50P614
Development Device MSP50P614
Functional Description for the MSP50C614
Functional Description for the MSP50C614
Functional Description for the MSP50C614
Crystal Reference Oscillator Connections
Resistor Trim Oscillator Connections
Reset Circuit
MSP50C601, MSP50C604, and MSP50C605
MSP50C601, MSP50C604, and MSP50C605
Page
MSP50C6xx Architecture
Architecture Overview
MSP50C6xx Core Processor Block Diagram
MSP50C6xx Architecture
Computational Unit Block Diagram
Signed and Unsigned Integer Representation
Computation Unit
Multiplier
Computation Unit
Computation Unit
Overview of the Multiplier Unit Operation
Arithmetic Logic Unit
Accumulator Block
Overview of the Arithmetic Logic Unit
Points to Offset
AC Register #
Points to
Data Memory Address Unit
Data Memory Address Unit
RAM Configuration
Data Memory Address Unit
Data Memory Addressing Modes
Program Counter Unit
Program Counter Unit
Bit Logic Unit
Memory Organization RAM and ROM
Memory Organization RAM and ROM
Memory Map
C6xx Memory Map not drawn to scale
Peripheral Communications Ports
Reset LOW
Summary of MSP50C614’s Peripheral Communications Ports
Interrupt Name ROM address Event Source Interrupt Priority
Summary of C614’s Peripheral Communications Ports
Interrupt Vectors
ROM Code Security
Write only
Block Protection Word
Address 0x7FFE
True Protection Marker N TM
≡ the binary complement of N TM
= the value programmed at TM5 … TM0 true
Protection marker
= the value programmed at FM5 … FM0 false
Interrupt Logic
Interrupt Logic
Macro Call Vectors
Bit wide location 00 ← INT number
IFR
Interrupt Logic
Interrupt Initialization Sequence
PLL Performance
Clock Control
Oscillator Options
Clock Control
PLL Performance
Clock Speed Control Register
Clock frequency kHz = Pllm register value + 1 ⋅ 65.536 kHz
RTO Oscillator Trim Adjustment
ClkSpdCtrl register
Rtrim Register Read Only Applies to MSP50C6xx Device Only
ClkSpdCtrl Value Copied Shaded
Timer Registers
Timer Registers
Timer Registers
Reduced Power Modes
Reduced Power Modes
Reduced Power Modes
Reduced Power Modes
Programmable Bits Needed to Control Reduced Power Modes
By Controls
Deeper sleep … relatively less power →
Component Determined
Deeper sleep …
Event Determined
Global interrupt enable is SET
Execution Timing
Execution Timing
Peripheral Functions
MSP50C614
I/O
General-Purpose I/O Ports
MSP50C604 MSP50C605
Peripheral Functions
Control register address 0x04h†
0x14h 0x1Ch 0x24h Possible control values = High-Z Input
Dedicated Input Port F
Data register address
Dedicated Output Port G
Input Port F
Branch on D Port
Totem-Pole Output Port G
Internal and External Interrupts
Interrupt Vector Source Trigger Event Priority Comment
Interrupts
Summary of the interrupts is given in Table
DAC Control and Data Registers
Digital-to-Analog Converter DAC
Pulse-Density Modulation Rate
Digital-to-Analog Converter DAC
Overflow bits Least-significant data value Ignored bits
PDM Clock Divider
PDM Clock Divider
Digital-to-Analog Converter DAC
Example 3-1 -kHz Sampling Rate
DAC
Example 3-2 -kHz Sampling Rate
Comparator
INT6 INT7 TIMER1 Enable
Comparator
IntGenCtrl register
Interrupt/General Control Register
Interrupt/General Control Register
Address Bit wide location Low
Interrupt/General Control Register
Hardware Initialization States
Hardware Initialization States
Hardware Initialization States
Bit Bit Name Initialized Value Description
Assembly Language Instructions
Instruction Set Summary
Introduction
System Registers
System Registers
Assembly Language Instructions
Top of Stack, TOS
Postdecrement
Accumulators AC0-AC31
Product High Register PH
Product Low Register PL
Bit
Accumulator Pointers AP0-AP3
Indirect Register R0-R7
Bits 16
String Register STR
Status Register Stat
Status Register Stat
Function
Instruction Syntax and Addressing Modes
1 MSP50P614/MSP50C614 Instruction Syntax
Bit Opcode
Addressing Mode Encoding
Addressing Modes
Next a
Addressing Mode Bits and adrs Field Description
Rx Bit Description
MSP50P614/MSP50C614 Addressing Modes Summary
Auto Increment and Auto Decrement Modes
Flagadrs
Flag addressing mode encoding, flagadrs
Flag Repeat
Clocks Words Addressing Operation, † Syntax
Example
Immediate Addressing
Syntax
ADD AP0, 0x1A
Mulr *0x02A1
Direct Addressing
MOV *0x012F * 2, *A0
Memory Operand
SyntaxOperation
Indirect Addressing
Indirect Addressing Syntax
Rx x = 0 Address Memory Operand ++ -- ++R5
*R4++
Relative Addressing
MOV A2, *R0
Movb *R7++, A3
R6 page register Address Bit positive offset Operand
A0, *R3+R5
Rx x = 0 Address Index Register R5 Operand
MOV A3, *R6+0x10
Rx x = 0 Address Memory Operand
Or TF2, *R6+0x02
Flag Addressing
TF1, *0x20
XOR TF1, *R6+0x20
8 Tag/Flag Bits
Possible sources of confusion Consider the following code
TF1,*ram1 TF1 bit in Stat is set!?
Instruction Classification
10. Symbols and Explanation
Symbol Explanation
Instruction Classification
Next a Accumulator control bits as described in Table
11. Symbols and Explanation
11. Instruction Classification
Class Sub- Description
Class Sub Description
12. Classes and Opcode Definition
Class 1 Instructions Memory and Accumulator Reference
C1a ~A~
13. Class 1 Instruction Encoding
14. Class 1a Instruction Description
C1b
15. Class 1b Instruction Description
C1b Mnemonic Description
Class 2 Instructions Accumulator and Constant Reference
C2a Mnemonic Description
16. Class 2 Instruction Encoding
17. Class 2a Instruction Description
C2b Mnemonic Description
18. Class 2b Instruction Description
Class 3 Instruction Accumulator Reference
ADD An ~, An ~, imm16 , next a
Mnemonic Description
19. Class 3 Instruction Encoding
20. Class 3 Instruction Description
Subs An~, An~, An Modified ADD An~, An~, An , next a
ALU status is modified. String bit causes subtract with
Zero or be set equal to the sign bit Xsgm dependent
SUB a n~, a n~, PH , next a
Carry status CF
Is modified
PH msbs extended by XM mode bit. Transfer the lower
MOV SV, An~ , next a
From the offset accumulator A~=1 or accumulator
Class 4 Instructions Address Register and Memory Reference
21. Class 4a Instruction Encoding
24. Class 4c Instruction Description
22. Class 4a Instruction Description
23. Class 4b Instruction Description
25. Class 4d Instruction Description
27. Class 5 Instruction Description
Class 5 Instructions Memory Reference
26. Class 5 Instruction Encoding
Adrs. Transfer status is modified
Stag adrs
Dressing mode adrs. Transfer status is modified
MOV adrs, TOS
Tag bit
29. Class 6a Instruction Description
Class 6 Instructions Port and Memory Reference
28. Class 6a Instruction Encoding
C6a Mnemonic Description
C6b Mnemonic Description
30. Class 6b Instruction Description
Class 7 Instructions Program Control
Jcc
31. Class 7 Instruction Encoding and Description
Vector8
Ccc
Class 8 Instructions Logic and Bit
32. Class 8a Instruction Encoding
Class 9 Instructions Miscellaneous
33. Class 8a Instruction Description
34. Class 8b Instruction Description
C8a Mnemonic Description
37. Class 9b Instruction Description
35. Class 9a Instruction Encoding
36. Class 9a Instruction Description
C9a Mnemonic Description
39. Class 9d Instruction Description
Bit, Byte, Word and String Addressing
38. Class 9c Instruction Description
C9c Mnemonic Description
Word
Global Flags Relative
0000h 0001h 0002h 0040h 0041h Nnnn 17th Bit
0000h MS Byte LS Byte
Movb A0, *0x0003
Mode Address Used Data Order Rx Post modify †
40. Data Memory Address and Data Relationship
MOV A0, *0x0004
Which uses the absolute word memory address
Rflag
MSP50P614/MSP50C614 Computational Modes
MSP50P614/MSP50C614 Computational Modes
Computational Setting Resetting Function Mode Instruction
41. MSP50P614/MSP50C614 Computational Modes
SXM
Example 4.6.1 SXM
Example 4.6.1 Sovm
Example 4.6.2 Sovm
Hardware Loop Instructions
Hardware Loop Instructions
Completion of the BEGLOOP/ENDLOOP block
42. Hardware Loops in MSP50P614/MSP50C614
Syntax Operation Limitations
Data memory *address = data
String Instructions
43. Initial Processor State for String Instructions
Program memory *address = data
Mulapl A0, A0~
Lookup Instructions
Lookup Instructions
44. Lookup Instructions
Instructions Description Data Transfer
MOV An, adrs SUB An MOV An, *An
Input/Output Instructions
Input/Output Instructions
Special Filter Instructions
Xk-2 Xk+2 Xk-1 xk+1 32 or
Special Filter Instructions
Special Filter Instructions
STR,0
0x0106
0x0100 0x0102
0x0104
Go back N words to wrap around
After FIR/COR execution
Important Note About Setting the Stat Register
Firkcoeffs
FIR/COR only = 0..N
Coeffarray address FIRK/CORK only Program memory FIRK/CORK
Coeffarray Samplebuf address
Coeffarray
Samplebuf Coeffarray is stored
Conditionals
Conditionals
Offset16 ≤
Symbol Meaning
Operands
Port4 ≤ Port6 ≤
Dma n
Adrsn
Clk
Flg
Port n
Offset n
Pma n
47. Flag Addressing Syntax and BIts
46. Addressing Mode Bits and adrs Field Description
45. Auto Increment and Decrement
Individual Instruction Descriptions
Individual Instruction Descriptions
14.1 ADD Add word
Execution
Description
See Also
Opcode
Addb
PC PC + Flags Affected
Adds Add String
Clock , clk Words , w
Adds A1, A1~, A1
14.4 Bitwise
TF2, *0x0020
ANDS, ANDB, OR, ORB, ORS, XOR, XORB, Xors
A3, *R4
OF, SF, ZF, CF are set accordingly
Andb Bitwise and Byte
Src byte PC PC +
Clock , clk Word , w
Ands A0, A0~, *R2
Ands Bitwise and String
Ands A0, A0~, A0
Flags Affected None Opcode
Begloop Begin Loop
Save next instruction address PC +
Order to loop N times
Call Unconditional Subroutine Call
RET
NOP
14.9 Ccc
TOS
48. Names for cc
True condition Not true condition
Syntax Alternate Syntax Description
CTF1
CALL, VCALL, RET, Iret
0x2010
Crnbe
PC = PC + w
14.10 CMP Compare Two Words
Stat flags set by src src1 operation
CMPB, CMPS, Jcc, Ccc
CMP R2, 0xfe20
CMP R0, R5
Cmpb Compare Two Bytes
Cmpb R3
Cmps A1~
Cmps Compare Two Strings
PC PC + w Flags Affected
Cmps A2, A2~
An, *Rx 3nR+2
With RPT instruction. See .11 for more detail on the setup
14.13 COR Correlation Filter Function
Rxeven = Rxeven + R5
3n R+2
Cork Correlation Filter Function
Sample data. During Cork execution, interrupt is queued
Xeven = R xeven + R5
Argument, it assumes n =1
Endloop End Loop
Decrement R4 by n 1 or PC first address after Begloop else
BEGLOOP, Inte
Copy accumulator sign flag SF to all 16 bits of a n ~
Extsgn Sign Extend Word
~ , next a
Dest , mod
Extsgns Sign Extend String
An~
100
An, *Rx 2nR+2
Assembly Language Instructions 101
14.18 FIR FIR Filter Function Coefficients in RAM
Rxeven++
102
Assembly Language Instructions 103
Firk
Idle Halt Processor
104
A2~, 0x3d
14.21 Input From Port Into Word
INS, OUT, Outs
14.22 INS Input From Port Into String
IN, OUT, Outs
STAT.IM
Intd Interrupt Disable
Assembly Language Instructions 107
IM is Stat bit PC PC + Flags Affected None Opcode
INTD, Iret
Interrupt Enable
Inte
Clock, clk Word, w With RPT, clk Class
Assembly Language Instructions 109
Iret Return From Interrupt
Conditional Jumps
RCF and RZF affected by post-modification of R
Assembly Language Instructions 111
Cc names
If test condition is false, a NOP is executed
JE 0x2010, R3++R5
See Also JMP, CALL, C cc Example
JNZ
Jtag 0x2010, R2++
See Also Cc, CALL, C cc Example
14.27 JMP Unconditional Jump
Post-modify R x if specified
Instruction Operation
14.28 MOV Move Data Word From Source to Destination
TF n, cc , R
XSF, XZF are set accordingly
Clock , clk Word , w With RPT , clk Class
STR, imm8
Assembly Language Instructions 117
MOV adrs, DP
With some operand types
Example 4.14.28.11 MOV A1~, *A1
MOVU, MOVT, MOVB, MOVBS, Movs
Example 4.14.28.10 MOV MR, A3, --A
Example 4.14.28.12 MOV *0x0200 * 2, R0
Transfer R5 to R0 Example
Example 4.14.28.13 MOV R1, 0x0200
Example 4.14.28.15 MOV *0x0200 * 2, R0
Example 4.14.28.18 MOV *R6 + 8 * 2, DP
MOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs
Movaph Move With Adding PH
Execution An + PH
Background. See .8 for more details
Movaphs Move With Adding PH
Execution + PH
MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs
Movb A0, *R2
Movb Move Byte From Source to Destination
Copy value of unsigned src byte to dest byte
Copy data memory byte pointed by R2 to accumulator A0
Movb R2
Movb *R2, A0
Movb A0, 0xf2
Movbs A2, *0x0200
Movbs Move Byte String from Source to Destination
TAG bit is set to bit 17th value
Movbs *0x0200, A2
Adrs , An ~
Movs Move String from Source to Destination
An ~ , adrs
Adrs , *An
Movs A1, A1~
MOVU, MOV, MOVT, MOVB, Movbs
Movs A2~
Movs A1~, A1
128
Movsph
MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs
Movsphs Move String With Subtract From PH
An second word PH MR contents of adrs
Assembly Language Instructions 129
Details
Available
Movt
PC PC + w Flags Affected None Opcode
MOVU, MOV, MOVT, MOVB, MOVBS, Movs
MOV, MOVB, MOVT, MOVBS, Movs
Movu Move Data Unsigned
TAG bit is set accordingly UM is set to
Copy the value pointed by R3 to MR
132
MR/SV An S APn
Xxxxxx Xxxx00 Flag Bit
Accumulator pointer if specified
14.38 MUL Multiply Rounded
MR * src PC PC + w Flags Affected
MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl
MULS, MUL, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls
Mulr Multiply Rounded With No Data Transfer
MR * src PC PC + Flags Affected
Mulapl
Muls Multiply String With No Data Transfer
Length nS+2, where nS is the value in STR register
Assembly Language Instructions 135
PH,PL MR * src string
Background. See .8 for more detail
Mulapl Multiply and Accumulate Result
PH ,PL MR * src
MULAPLS, MULSPL, MULSPLS, MULTPL, Multpls
MULAPL, MULSPL, MULSPLS, MULTPL, Multpls
Mulapls Multiply String and Accumulate Result
MR * src
MULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls
Mulspl Multiply and Subtract PL From Accumulator
Occuring in the background. See .8 for more details
Syntax Description Mulspl adrs
MULSPL, MULTPL, MULTPLS, MULAPL, Mulapls
Mulspls Multiply String and Subtract PL From Accumulator
From dest string
Syntax Description Mulspls adrs
Value of src. The 16 MSBs
Multpl Multiply and Transfer PL to Accumulator
~ , a n ~ , next a
Multiply MR by data memory word, move PL to a n
MULTPL, MULAPL, MULAPLS, MULSPL, Mulspls
Multpls
Execution PH, PL MR * src PC PC + Flags Affected
Example 4.14.46.2 Multpls A2, A2~
NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs
Negac Two’s Complement Negation of Accumulator
Accumulator
Example 4.14.47.1 Negac A3~, A3, --A
Dest accumulator string
Assembly Language Instructions 143
Negacs Two’s Complement Negation of Accumulator String
NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs
RPT
14.49 NOP No Operation
Execution PC PC +
NEGAC, Negacs
Notac One’s Complement Negation of Accumulator
NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors
Example 4.14.50.1 Notac A3~, A3, --A
Negacs
Notacs One’s Complement Negation of Accumulator String
Accumulator string
A3~
Accumulator pointers are allowed with some operand types
14.52 or Bitwise Logical or
TFn bits in Stat register are set accordingly
Or TF1, *R6+0x22
ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs
Or A0, *R0++R5
148
Accumulator is affected
14.53 ORB Bitwise or Byte
Or src
OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs
OR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs
14.54 ORS Bitwise or String
PC + w Flags Affected
ORS A0, A0~, A0
OUTS, IN, INS
14.55 OUT
Address is multipled by 4 to get the actual port address
OUT, IN, INS
Outs Output String to Port
Port6 specified in the instruction
Port6 , An ~
R7 R7 Flags Affected
14.57 RET Return From Subroutine CALL, Ccc
PC TOS
CALL, i.e., RET followed by a RET should not be allowed
Example 4.14.58.2 Rflag *R6 +
Rflag Reset Memory Flag
Sflag , Stag , Rtag
14.59 RFM
Reset Fractional Mode Syntax
Resets the fractional mode. Clears FM bit of Stat
STAT.FM
Resets the overflow mode to zero
Rovm Reset Overflow Mode
Saturation output normal mode
Stat .OM
Load imm8 to repeat counter
14.61 RPT Repeat Next Instruction
If RPT adrs8 Load src to repeat counter
After execution completes
Rtag *R6+0x0002
Rtag Reset Tag
Stag , Rflag , Sflag
Rtag *R6+0x0003
STAT.XM
14.63 RXM Reset Extended Sign Mode
Assembly Language Instructions 159
SXM
Rflag , Stag , Rtag
Address flagadrs only accesses the 17 th bit
Sflag Set Memory Flag
160
Assembly Language Instructions 161
14.65 SFM Set Fractional Mode
Mode for signed fractional arithmetic
Set fractional mode. Set FM bit of Stat to
Accumulator. Use Shlac for this purpose
14.66 SHL Shift Left
PH , PL
Shls
Shift accumulator A1 by one bit to the left
Shlac Shift Left Accumulator
Its offset. LSB of result is set to zero
Example 4.14.67.2 Shlac A1~, A1, --A
164
Shlacs Shift Left Accumulator String Individually
Accumulators in the string
Shlapl A2, *R1++
Shlapl Shift Left with Accumulate
Example 4.14.69.1 Shlapl A0, *R4++R5
Example 4.14.69.3 Shlapl A1, A1, ++A
Shift a n ~ string left, addb PL to a n ~
Shlapls Shift Left String With Accumulate
Shift data memory string left, add PL to a n
Execution PH, PL
Assembly Language Instructions 167
Shls Shift Left Accumulator String to Product
An~
Shlspl A2, *R1++
Shlspl Shift Left With Subtract PL
Example 4.14.72.1 Shlspl A0, *R4++R5
Example 4.14.72.3 Shlspl A1, A1, ++A
NS+3 NR+3
Assembly Language Instructions 169
Shlspls Shift Left String With Subtract PL
Shift RAM string left, subtract PL from An
Shltpl A2, *R1++
Shltpl Shift Left and Transfer PL to Accumulator
Example 4.14.74.1 Shltpl A0, *R4++R5
Example 4.14.74.3 Shltpl A1, A1, ++A
SHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls
Shltpls Shift Left String and Transfer PL to Accumulator
Receives the same data as PH
Shift the accumulator string A1 by nSV bits to the left
Shift right one bit the accumulator A1
Shrac Shift Accumulator Right
Register
Example 4.14.76.2 Shrac A1~, A1, ++A
SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl
Assembly Language Instructions 173
Shracs Shift Accumulator String Right
Shltpls
Sovm
Set Overflow Mode Syntax
Output DSP mode
STAT.OM
Stag *0x401
Stag
RTAG, RFLAG, Sflag
An ~ , An , adrs , next a
14.80 SUB Subtract
Dest, src , src1 , next a
An ~ , An ~ , imm16 , next a
SUB A3~, A3, *R4
Example 4.14.80.2 SUB A0, A0, 2, ++A
SUB A1, A1~, A1
SUB R3, R5
Subtract 0xF2 from register R3 byte
Subb Subtract Byte
Subtract 0x45 from accumulator A2 byte
Syntax Description Subb a n, imm8
NR+2
Assembly Language Instructions 179
Subs Subtract Accumulataor String
Subs A3~, A3~, PH
Subs A2, A2, A2~
Subs A2, A2~, A2
180
Assembly Language Instructions 181
14.83 SXM Set Extended Sign Mode
Sets extended sign mode status register Stat bit 0 to
RXM
R7 R7 + Flags Affected
Vcall Vectored Call
Push PC + 0x7F00
See Also RET, IRET, CALL, C cc Example
XOR src For three operands
14.85 XOR Logical XOR
XOR src For two operands
TAG bit is set accordingly Src is flagadrs
Example 4.14.85.2 XOR A0, A0, 2, ++A
XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Example 4.14.85.1 XOR A1, A1, 0x13FF
XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Assembly Language Instructions 185
Xorb Logical XOR Byte
XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Xors Logical XOR String
Dest string
Xors A2, A2~, A2
Zacs
14.88 ZAC Zero Accumulator
PC PC + Flags Affected ZF =
ZAC A1~, ++A
Zero the specified accumulator string
Reset the content of offset accumulator string A1~ to zero
Zacs Zero Accumulator String
ZAC
Instruction Set Encoding
Assembly Language Instructions 189
Instruction Set Encoding
190
Assembly Language Instructions 191
192
Assembly Language Instructions 193
194
Assembly Language Instructions 195
196
Assembly Language Instructions 197
Description True condition Not true condition
Instruction Set Summary
An~, pma16
Pma16 , Rmod Assembly Language Instructions 199
An~, An~ , next a
An, An~
An ~, imm16 , next a
Adrs, a n~ , next a
~, adrs , next a
MR , imm16 , next a
STR, adrs
Assembly Language Instructions 201
Adrs, TOS
Flagadrs† , TFn
~ , a n~
~ , next a
~, a n~ , next a
Adrs An ~, An ~, imm16 , next a ~, a n~, a n , next a
An~, An~, pma16
An~, An~ , next a NR+3 Assembly Language Instructions 203
TFn, flagadrs NR+3 TFn, cc , Rx
An~, An~, An
~, a n, a n~
~, a n~
~, a n, a n~ , next a
~, a n~, PH
Conditional on RZF=1 Not condition RZF=0
Conditional on RCF=1 Not condition RCF=0
Conditional on RZF=0 and RCF=1 Not condition RZF≠ 0 or RCF≠
Conditional on ZF=0 and SF=1 Not condition ZF≠ Or SF≠
206Assembly Language Instructions
Instruction Set Summay
MC = Pllm value+1 ⋅ 131.07 kHz
208Assembly Language Instructions
Summay
Language Instructions
209
Instruction Set Summay 210Assembly Language Instructions
Code Development Tools
Introduction
Pin IDC Connector top view looking at the board
Code Development Tools
SDK50P614 kit of 15 MSP50P614s
MSP50C6xx Development Tools Guidelines
Categories of MSP50Cxx Development Tools
MSP50C6xx Development Tools Guidelines
Tools Definitions
SPEECH-EVM†PC50C604†
MSP50C6xx Development Tools Guidelines
Software Tools-Definitions
System Requirements
MSP50C6xx Code Development Tools
Documentation
Hardware Tools Setup
Red MSPSCANPORTI/F power Yellow
Green Target board power
Examples
Assembler
Assembler Directives
Assembler
An assembly language program
#ELSE see #IF and #IFDEF
Do other things here
#IF expression Do something here
#ELSE
#ENDIF
Example #IFDEF symbol
#IFNDEF symbol
Assembler
Compiler
Compiler
Foreword
Type Name Mnemonic Range Size in Bytes Example
Variable Types
External References
Without Arguments
Defines a replacement string for a given string
Directives
With Arguments
Include Files
See #if directive
#define STRLENGTHi Major Differences between C and C
RAM Usage
Function Prototypes and Declarations
Initializations
Initialization values are stored in program memory
Operator can take the following values predefined constants
String Functions
String Functions
Constant Functions
An example of the use of xferconst is
This section is C- specific
Implementation Details
Comparisons
Signed comparison of a and b. a is in A0, b is in A0~
Ult
Assembly Vector
Unsigned comparison of a and b. a is in A0, b is in A0~
Ugt
Stack frame has the following structure
Division
Function Calls
Low Address High Address
On Call
Programming Example
Cmmfunc bidonint i1,char *i2 is valid, but
On RET
#include cmmmacr.h
Programming Example, C -- With Assembly Routines
Reserved
Implementation Details
R7Param
Addb R7,2
To C function return in roncoreturn
OldR5 Return Addr Param R7,R5 Stack data
Param R7,R5 Stack data Before call Parameter
Return Addr Param Stack data
Efficiency
Efficiency
To ASM function return
Efficiency
Real Time Clock Example
Example 5-1. First Project
Jrtc.rpj Hmodules
Allocated by changing
MAINRAM.IRX
Efficiency
CMM1.ASM
Sixth file, cmm1ram.asm, allocates memory for cmm1.asm
Allocated as follows
MAIN.CMM
Example 5-2. Second Project C-- With Speech
Dspvar.irx dsputil.asm getbits.asm speak.asm speak.irx
Celp Celp.irx
Util.obj
Isr Tim2isr.asm dacisr.asm J tim1isr.asm
Ampm.qfm
Tens.qfm
Melp
Dsp
Ramendcustomer Ramstartcustomer
Clock will need to say
Assembly routines that will be called are declared external
New C-- callable functions were declared global
Cmmfunc speakHours
Example 5-3. Third Project C-- with an LCD
Celp Ampm.qfm Days.qfm Ones.qfm Teens.qfm
Melp.irx Melp.obj
Lcd Lcd.asm Lcd.irx
External lcdsetio external lcdinit
Case
Efficiency
Beware of Stack Corruption
Beware of Stack Corruption
Reported Bugs With Code Development Tool
Reported Bugs With Code Development Tool
Applications
Application Circuits
Application Circuits
3300 pF
∝ F 22 pF
MSP50P614 only 100 kΩ
Applications6-3
Initializing the MSP50C6xx
Initializing the MSP50C6xx
File init.asm
Applications6-5
JNZ Itsacpart Itsappart
Applications6-7
TI-TALKS Example Code
TI-TALKS Example Code
Getting Started
RAM Overlay
RAM Overlay
Creating a New Project
Applications6-9
RAM Overlay
Adding Customer Variables
Common Problems
Page
Customer Information
Package Information
Mechanical Information
Die Bond-Out Coordinates
Signal and Pad Descriptions for the MSP50C614
Customer Information
Signal and Pad Descriptions for the MSP50C605
Signal and Pad Descriptions for the MSP50C601
Signal and Pad Descriptions for the MSP50C604
Pin QFP Mechanical Information
13 NOM
13 12 11 10 9 8 7 6 5 4 3 2
Extra pin 3 4 5 6 7 8 9 10 11 12 13 Bottom View
Bottom View of 120-Pin PGA Package of the MSP50P614
Bottom view
0x0006 Device number 0x0614
Customer Information Fields in the ROM
Customer Information Fields in the ROM
Device Production Sequence
Speech Specification
Speech Development Cycle
Software Design Hardware Design
Device Production Sequence
6xx
Ordering Information
New Product Release Forms Nprf
Code Letter PJM Loopin 100-Pin QFP
New Product Release Forms Nprf
Approval of Prototypes and Authorization to Start Production
NEW Product Release Form for MSP50C604 Option Selection
New Product Release Forms Nprf
NEW Product Release Form for MSP50C605 Option Selection
New Product Release Forms Nprf
NEW Product Release Form for MSP50C601 Option Selection
New Product Release Forms Nprf
Additional Information
Topic
Additional Information
Additional Information