Dedicated Input Port F | Texas Instruments MSP50C6xx specs

I/O

The following table shows the bit locations of the I/O port mapping:

			(8-bit wide location)
			07	06	05	04	03	02	01	00

A port data register . . . . . address 0x00			A7	A6	A5	A4	A3	A2	A1	A0

A port control register . . . address 0x04			C	C	C	C	C	C	C	C

B port data register . . . . . address 0x08			B7	B6	B5	B4	B3	B2	B1	B0

B port control register . . . address 0x0C			C	C	C	C	C	C	C	C

C port data register . . . . . address 0x10			C7	C6	C5	C4	C3	C2	C1	C0

C port control register . . . address 0x14			C	C	C	C	C	C	C	C

D port data register . . . . . address 0x18			D7	D6	D5	D4	D3	D2	D1	D0

D port control register† . . address 0x1C			C	C	C	C	C	C	C	C

E port data register . . . . . address 0x20			E7	E6	E5	E4	E3	E2	E1	E0

E port control register . . . address 0x24			C	C	C	C	C	C	C	C

A7, B7, C7, D7, E7	: data register
C	: control register (0 = IN, 1 = OUT)
0x00 : state of control register after RESET low

†Ports D4 and D5 may be dedicated to the Comparator function, if the Comparator Enable bit is set. If so, then bits 4 and 5 of the D port Control register must be CLEAR. Please refer to Section 3.3, Comparator, for details.

Port D0 is connected to the branch condition COND1. Port D1 is connected to the branch condition COND2, assuming the comparator is disabled. Please refer to Section 3.1.4, Branch on D Port, (and to Section 3.3, Comparator) for more information. External interrupts can be detected when transitions occur on ports D2, D3, D4, and D5. The interrupts associated with the D port are supported whether those pins are programmed as inputs or as outputs.

3.1.2Dedicated Input Port F

Port F is an 8-bit wide input-only port. The data presented to the input pin can be read by referring to the appropriate bit in the F port data register, address 0x28. This is done using the IN instruction, with the 0x28 address as an argument. The state of the F port data registers is not initialized with RESET. After RESET is taken high, the state of the F port data register is unknown.

Each of the pins at port F has a programmable pull-up resistor. All eight pullup resistors can be enabled by setting the enable pullup (EP) in the interrupt/gen- eral control register (IntGenCtrl). The address of the IntGenCtrl is 0x38, and the location of the EP bit is 12. Clearing the EP bit disables the eight pullups,

3-4

Image 68

Texas Instruments MSP50C6xx manual Dedicated Input Port F

Contents

MSP50C6xx Mixed-Signal Processor User’s Guide Important Notice How to Use This Manual About This ManualNotational Conventions Iii Notational Conventions Here is a sample program listingCsr -a /user/ti/simuboard/utilities Information About Cautions and Warnings TrademarksThis book may contain cautions and warnings Information About Cautions and WarningsPage Contents Peripheral Functions Assembly Language InstructionsContents Contentsix Code Development Tools Applications Customer Information Contentsxi PLL Performance -27 2-10 Instruction Execution and Timing Tables Contentsxiii Tables Xiv Introduction to the MSP50C6xx Features of the MSP50C6xx Features of the MSP50C6xx Applications Consumer EducationIndustrial Aids for the Handicapped Development Device MSP50P614 Development Device MSP50P614 Functional Description for the MSP50C614 Functional Description for the MSP50C614 Functional Description for the MSP50C614 Crystal Reference Oscillator Connections Resistor Trim Oscillator Connections Reset Circuit MSP50C601, MSP50C604, and MSP50C605 MSP50C601, MSP50C604, and MSP50C605Page MSP50C6xx Architecture Architecture Overview MSP50C6xx Core Processor Block Diagram MSP50C6xx Architecture Computational Unit Block Diagram Computation Unit MultiplierSigned and Unsigned Integer Representation Computation Unit Computation Unit Overview of the Multiplier Unit Operation Arithmetic Logic Unit Accumulator Block Overview of the Arithmetic Logic Unit Points to Offset AC Register #Points to Data Memory Address Unit Data Memory Address Unit RAM Configuration Data Memory Address Unit Data Memory Addressing Modes Program Counter Unit Program Counter UnitBit Logic Unit Memory Organization RAM and ROM Memory Organization RAM and ROMMemory Map C6xx Memory Map not drawn to scale Peripheral Communications Ports Reset LOW Summary of MSP50C614’s Peripheral Communications Ports Interrupt Name ROM address Event Source Interrupt Priority Summary of C614’s Peripheral Communications PortsInterrupt Vectors ROM Code Security Block Protection Word Address 0x7FFEWrite only True Protection Marker N TM = the value programmed at TM5 … TM0 true Protection marker≡ the binary complement of N TM = the value programmed at FM5 … FM0 false Interrupt Logic Interrupt LogicMacro Call Vectors Bit wide location 00 ← INT number IFR Interrupt Logic Interrupt Initialization Sequence Clock Control Oscillator OptionsPLL Performance Clock Control PLL Performance Clock Speed Control Register Clock frequency kHz = Pllm register value + 1 ⋅ 65.536 kHz RTO Oscillator Trim Adjustment ClkSpdCtrl register Rtrim Register Read Only Applies to MSP50C6xx Device Only ClkSpdCtrl Value Copied Shaded Timer Registers Timer Registers Timer Registers Reduced Power Modes Reduced Power Modes Reduced Power Modes Reduced Power Modes Programmable Bits Needed to Control Reduced Power Modes By Controls Deeper sleep … relatively less power →Component Determined Deeper sleep … Event Determined Global interrupt enable is SET Execution Timing Execution Timing Peripheral Functions I/O General-Purpose I/O PortsMSP50C614 MSP50C604 MSP50C605 Peripheral Functions Control register address 0x04h†0x14h 0x1Ch 0x24h Possible control values = High-Z Input Dedicated Input Port F Data register address Dedicated Output Port GInput Port F Branch on D Port Totem-Pole Output Port G Internal and External Interrupts Interrupt Vector Source Trigger Event Priority Comment InterruptsSummary of the interrupts is given in Table Digital-to-Analog Converter DAC Pulse-Density Modulation RateDAC Control and Data Registers Digital-to-Analog Converter DAC Overflow bits Least-significant data value Ignored bits PDM Clock Divider PDM Clock Divider Digital-to-Analog Converter DAC Example 3-1 -kHz Sampling Rate DAC Example 3-2 -kHz Sampling Rate Comparator INT6 INT7 TIMER1 Enable Comparator Interrupt/General Control Register Interrupt/General Control RegisterIntGenCtrl register Address Bit wide location Low Interrupt/General Control Register Hardware Initialization States Hardware Initialization States Hardware Initialization States Bit Bit Name Initialized Value Description Assembly Language Instructions Instruction Set Summary Introduction System Registers Assembly Language Instructions Top of Stack, TOSSystem Registers Postdecrement Accumulators AC0-AC31 Product High Register PHProduct Low Register PL Accumulator Pointers AP0-AP3 Indirect Register R0-R7Bit Bits 16 String Register STR Status Register Stat Status Register Stat Function Instruction Syntax and Addressing Modes 1 MSP50P614/MSP50C614 Instruction Syntax Addressing Mode Encoding Addressing ModesBit Opcode Next a Addressing Mode Bits and adrs Field Description Rx Bit Description MSP50P614/MSP50C614 Addressing Modes Summary Auto Increment and Auto Decrement Modes Flag addressing mode encoding, flagadrs Flag RepeatFlagadrs Clocks Words Addressing Operation, † Syntax Immediate Addressing SyntaxExample ADD AP0, 0x1A Direct Addressing MOV *0x012F * 2, *A0Mulr *0x02A1 Memory Operand Indirect Addressing Indirect Addressing SyntaxSyntaxOperation Rx x = 0 Address Memory Operand ++  --  ++R5 Relative Addressing MOV A2, *R0*R4++ Movb *R7++, A3 R6 page register Address Bit positive offset Operand A0, *R3+R5Rx x = 0 Address Index Register R5 Operand MOV A3, *R6+0x10 Rx x = 0 Address Memory Operand Flag Addressing TF1, *0x20Or TF2, *R6+0x02 XOR TF1, *R6+0x20 8 Tag/Flag Bits Possible sources of confusion Consider the following code TF1,*ram1 TF1 bit in Stat is set!? 10. Symbols and Explanation Symbol ExplanationInstruction Classification Instruction Classification 11. Symbols and Explanation 11. Instruction ClassificationNext a Accumulator control bits as described in Table Class Sub- Description Class Sub Description 12. Classes and Opcode Definition Class 1 Instructions Memory and Accumulator Reference 13. Class 1 Instruction Encoding 14. Class 1a Instruction DescriptionC1a ~A~ C1b 15. Class 1b Instruction Description C1b Mnemonic Description Class 2 Instructions Accumulator and Constant Reference C2a Mnemonic Description 16. Class 2 Instruction Encoding17. Class 2a Instruction Description 18. Class 2b Instruction Description Class 3 Instruction Accumulator ReferenceC2b Mnemonic Description ADD An ~, An ~, imm16 , next a 19. Class 3 Instruction Encoding 20. Class 3 Instruction DescriptionMnemonic Description Subs An~, An~, An Modified ADD An~, An~, An , next a Zero or be set equal to the sign bit Xsgm dependent SUB a n~, a n~, PH , next aALU status is modified. String bit causes subtract with Carry status CF PH msbs extended by XM mode bit. Transfer the lower MOV SV, An~ , next aIs modified From the offset accumulator A~=1 or accumulator Class 4 Instructions Address Register and Memory Reference 21. Class 4a Instruction Encoding 22. Class 4a Instruction Description 23. Class 4b Instruction Description24. Class 4c Instruction Description 25. Class 4d Instruction Description Class 5 Instructions Memory Reference 26. Class 5 Instruction Encoding27. Class 5 Instruction Description Adrs. Transfer status is modified Dressing mode adrs. Transfer status is modified MOV adrs, TOSStag adrs Tag bit Class 6 Instructions Port and Memory Reference 28. Class 6a Instruction Encoding29. Class 6a Instruction Description C6a Mnemonic Description C6b Mnemonic Description 30. Class 6b Instruction DescriptionClass 7 Instructions Program Control 31. Class 7 Instruction Encoding and Description Vector8Jcc Ccc Class 8 Instructions Logic and Bit 32. Class 8a Instruction Encoding 33. Class 8a Instruction Description 34. Class 8b Instruction DescriptionClass 9 Instructions Miscellaneous C8a Mnemonic Description 35. Class 9a Instruction Encoding 36. Class 9a Instruction Description37. Class 9b Instruction Description C9a Mnemonic Description Bit, Byte, Word and String Addressing 38. Class 9c Instruction Description39. Class 9d Instruction Description C9c Mnemonic Description Global Flags Relative 0000h 0001h 0002h 0040h 0041h Nnnn 17th BitWord 0000h MS Byte LS Byte Mode Address Used Data Order Rx Post modify † 40. Data Memory Address and Data RelationshipMovb A0, *0x0003 MOV A0, *0x0004 Which uses the absolute word memory address Rflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational Modes Computational Setting Resetting Function Mode Instruction 41. MSP50P614/MSP50C614 Computational Modes SXM Example 4.6.1 SXM Example 4.6.1 SovmExample 4.6.2 Sovm Hardware Loop Instructions Hardware Loop Instructions Completion of the BEGLOOP/ENDLOOP block 42. Hardware Loops in MSP50P614/MSP50C614Syntax Operation Limitations String Instructions 43. Initial Processor State for String InstructionsData memory *address = data Program memory *address = data Mulapl A0, A0~ Lookup Instructions 44. Lookup InstructionsLookup Instructions Instructions Description Data Transfer MOV An, adrs SUB An MOV An, *An Input/Output Instructions Special Filter InstructionsInput/Output Instructions Xk-2 Xk+2 Xk-1 xk+1 32 or Special Filter Instructions Special Filter Instructions STR,0 0x0100 0x0102 0x01040x0106 Go back N words to wrap around After FIR/COR execution Important Note About Setting the Stat Register Firkcoeffs Coeffarray address FIRK/CORK only Program memory FIRK/CORK Coeffarray Samplebuf addressFIR/COR only = 0..N Coeffarray Samplebuf Coeffarray is stored Conditionals Conditionals Symbol Meaning OperandsOffset16 ≤ Port4 ≤ Port6 ≤ Adrsn ClkDma n Flg Port n Offset nPma n 47. Flag Addressing Syntax and BIts 46. Addressing Mode Bits and adrs Field Description45. Auto Increment and Decrement Individual Instruction Descriptions Individual Instruction Descriptions 14.1 ADD Add word Execution Description See Also Opcode AddbPC PC + Flags Affected Adds Add String Clock , clk Words , w Adds A1, A1~, A1 14.4 Bitwise TF2, *0x0020 ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XorsA3, *R4 Andb Bitwise and Byte Src byte PC PC +OF, SF, ZF, CF are set accordingly Clock , clk Word , w Ands A0, A0~, *R2 Ands Bitwise and StringAnds A0, A0~, A0 Begloop Begin Loop Save next instruction address PC +Flags Affected None Opcode Order to loop N times Call Unconditional Subroutine Call RET NOP 14.9 CccTOS 48. Names for cc True condition Not true condition Syntax Alternate Syntax Description CALL, VCALL, RET, Iret 0x2010CTF1 Crnbe 14.10 CMP Compare Two Words Stat flags set by src src1 operationPC = PC + w CMPB, CMPS, Jcc, Ccc CMP R2, 0xfe20 CMP R0, R5 Cmpb Compare Two Bytes Cmpb R3 Cmps Compare Two Strings PC PC + w Flags AffectedCmps A1~ Cmps A2, A2~ With RPT instruction. See .11 for more detail on the setup 14.13 COR Correlation Filter FunctionAn, *Rx 3nR+2 Rxeven = Rxeven + R5 Cork Correlation Filter Function Sample data. During Cork execution, interrupt is queued3n R+2 Xeven = R xeven + R5 Endloop End Loop Decrement R4 by n 1 or PC first address after Begloop elseArgument, it assumes n =1 BEGLOOP, Inte Extsgn Sign Extend Word ~ , next aCopy accumulator sign flag SF to all 16 bits of a n ~ Dest , mod Extsgns Sign Extend String An~ 100 Assembly Language Instructions 101 14.18 FIR FIR Filter Function Coefficients in RAMAn, *Rx 2nR+2 Rxeven++ 102 Assembly Language Instructions 103 Firk Idle Halt Processor 104 A2~, 0x3d 14.21 Input From Port Into WordINS, OUT, Outs 14.22 INS Input From Port Into String IN, OUT, Outs Intd Interrupt Disable Assembly Language Instructions 107STAT.IM IM is Stat bit PC PC + Flags Affected None Opcode Interrupt Enable InteINTD, Iret Clock, clk Word, w With RPT, clk Class Assembly Language Instructions 109 Iret Return From Interrupt Conditional Jumps RCF and RZF affected by post-modification of R Assembly Language Instructions 111 Cc names If test condition is false, a NOP is executed See Also JMP, CALL, C cc Example JNZJE 0x2010, R3++R5 Jtag 0x2010, R2++ 14.27 JMP Unconditional Jump Post-modify R x if specifiedSee Also Cc, CALL, C cc Example Instruction Operation 14.28 MOV Move Data Word From Source to Destination XSF, XZF are set accordingly Clock , clk Word , w With RPT , clk ClassTF n, cc , R STR, imm8 Assembly Language Instructions 117 MOV adrs, DP With some operand types MOVU, MOVT, MOVB, MOVBS, Movs Example 4.14.28.10 MOV MR, A3, --AExample 4.14.28.11 MOV A1~, *A1 Example 4.14.28.12 MOV *0x0200 * 2, R0 Example 4.14.28.13 MOV R1, 0x0200 Example 4.14.28.15 MOV *0x0200 * 2, R0Transfer R5 to R0 Example Example 4.14.28.18 MOV *R6 + 8 * 2, DP MOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs Movaph Move With Adding PHExecution An + PH Movaphs Move With Adding PH Execution + PHBackground. See .8 for more details MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs Movb Move Byte From Source to Destination Copy value of unsigned src byte to dest byteMovb A0, *R2 Copy data memory byte pointed by R2 to accumulator A0 Movb R2 Movb *R2, A0Movb A0, 0xf2 Movbs Move Byte String from Source to Destination TAG bit is set to bit 17th valueMovbs A2, *0x0200 Movbs *0x0200, A2 Movs Move String from Source to Destination An ~ , adrsAdrs , An ~ Adrs , *An MOVU, MOV, MOVT, MOVB, Movbs Movs A2~Movs A1, A1~ Movs A1~, A1 128 MovsphMOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs An second word PH MR contents of adrs Assembly Language Instructions 129Movsphs Move String With Subtract From PH Details Movt PC PC + w Flags Affected None OpcodeAvailable MOVU, MOV, MOVT, MOVB, MOVBS, Movs Movu Move Data Unsigned TAG bit is set accordingly UM is set toMOV, MOVB, MOVT, MOVBS, Movs Copy the value pointed by R3 to MR 132 MR/SV An S APnXxxxxx Xxxx00 Flag Bit 14.38 MUL Multiply Rounded MR * src PC PC + w Flags AffectedAccumulator pointer if specified MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl Mulr Multiply Rounded With No Data Transfer MR * src PC PC + Flags AffectedMULS, MUL, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls Mulapl Length nS+2, where nS is the value in STR register Assembly Language Instructions 135Muls Multiply String With No Data Transfer PH,PL MR * src string Mulapl Multiply and Accumulate Result PH ,PL MR * srcBackground. See .8 for more detail MULAPLS, MULSPL, MULSPLS, MULTPL, Multpls MULAPL, MULSPL, MULSPLS, MULTPL, Multpls Mulapls Multiply String and Accumulate ResultMR * src Mulspl Multiply and Subtract PL From Accumulator Occuring in the background. See .8 for more detailsMULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspl adrs Mulspls Multiply String and Subtract PL From Accumulator From dest stringMULSPL, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspls adrs Multpl Multiply and Transfer PL to Accumulator ~ , a n ~ , next aValue of src. The 16 MSBs Multiply MR by data memory word, move PL to a n Multpls Execution PH, PL MR * src PC PC + Flags AffectedMULTPL, MULAPL, MULAPLS, MULSPL, Mulspls Example 4.14.46.2 Multpls A2, A2~ Negac Two’s Complement Negation of Accumulator AccumulatorNEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Example 4.14.47.1 Negac A3~, A3, --A Assembly Language Instructions 143 Negacs Two’s Complement Negation of Accumulator StringDest accumulator string NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs RPT 14.49 NOP No OperationExecution PC PC + Notac One’s Complement Negation of Accumulator NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, XorsNEGAC, Negacs Example 4.14.50.1 Notac A3~, A3, --A Notacs One’s Complement Negation of Accumulator String Accumulator stringNegacs A3~ Accumulator pointers are allowed with some operand types 14.52 or Bitwise Logical orTFn bits in Stat register are set accordingly ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs Or A0, *R0++R5Or TF1, *R6+0x22 148 14.53 ORB Bitwise or Byte Or srcAccumulator is affected OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs 14.54 ORS Bitwise or String PC + w Flags AffectedOR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs ORS A0, A0~, A0 OUTS, IN, INS 14.55 OUTAddress is multipled by 4 to get the actual port address Outs Output String to Port Port6 specified in the instructionOUT, IN, INS Port6 , An ~ 14.57 RET Return From Subroutine CALL, Ccc PC TOSR7 R7 Flags Affected CALL, i.e., RET followed by a RET should not be allowed Example 4.14.58.2 Rflag *R6 + Rflag Reset Memory FlagSflag , Stag , Rtag Reset Fractional Mode Syntax Resets the fractional mode. Clears FM bit of Stat14.59 RFM STAT.FM Rovm Reset Overflow Mode Saturation output normal modeResets the overflow mode to zero Stat .OM 14.61 RPT Repeat Next Instruction If RPT adrs8 Load src to repeat counterLoad imm8 to repeat counter After execution completes Rtag Reset Tag Stag , Rflag , SflagRtag *R6+0x0002 Rtag *R6+0x0003 14.63 RXM Reset Extended Sign Mode Assembly Language Instructions 159STAT.XM SXM Address flagadrs only accesses the 17 th bit Sflag Set Memory FlagRflag , Stag , Rtag 160 14.65 SFM Set Fractional Mode Mode for signed fractional arithmeticAssembly Language Instructions 161 Set fractional mode. Set FM bit of Stat to 14.66 SHL Shift Left PH , PLAccumulator. Use Shlac for this purpose Shls Shlac Shift Left Accumulator Its offset. LSB of result is set to zeroShift accumulator A1 by one bit to the left Example 4.14.67.2 Shlac A1~, A1, --A 164 Shlacs Shift Left Accumulator String IndividuallyAccumulators in the string Shlapl Shift Left with Accumulate Example 4.14.69.1 Shlapl A0, *R4++R5Shlapl A2, *R1++ Example 4.14.69.3 Shlapl A1, A1, ++A Shift a n ~ string left, addb PL to a n ~ Shlapls Shift Left String With AccumulateShift data memory string left, add PL to a n Assembly Language Instructions 167 Shls Shift Left Accumulator String to ProductExecution PH, PL An~ Shlspl Shift Left With Subtract PL Example 4.14.72.1 Shlspl A0, *R4++R5Shlspl A2, *R1++ Example 4.14.72.3 Shlspl A1, A1, ++A Assembly Language Instructions 169 Shlspls Shift Left String With Subtract PLNS+3 NR+3 Shift RAM string left, subtract PL from An Shltpl Shift Left and Transfer PL to Accumulator Example 4.14.74.1 Shltpl A0, *R4++R5Shltpl A2, *R1++ Example 4.14.74.3 Shltpl A1, A1, ++A Shltpls Shift Left String and Transfer PL to Accumulator Receives the same data as PHSHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls Shift the accumulator string A1 by nSV bits to the left Shrac Shift Accumulator Right RegisterShift right one bit the accumulator A1 Example 4.14.76.2 Shrac A1~, A1, ++A Assembly Language Instructions 173 Shracs Shift Accumulator String RightSHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl Shltpls Set Overflow Mode Syntax Output DSP modeSovm STAT.OM Stag *0x401 StagRTAG, RFLAG, Sflag 14.80 SUB Subtract Dest, src , src1 , next aAn ~ , An , adrs , next a An ~ , An ~ , imm16 , next a Example 4.14.80.2 SUB A0, A0, 2, ++A SUB A1, A1~, A1SUB A3~, A3, *R4 SUB R3, R5 Subb Subtract Byte Subtract 0x45 from accumulator A2 byteSubtract 0xF2 from register R3 byte Syntax Description Subb a n, imm8 NR+2 Assembly Language Instructions 179Subs Subtract Accumulataor String Subs A2, A2, A2~ Subs A2, A2~, A2Subs A3~, A3~, PH 180 14.83 SXM Set Extended Sign Mode Sets extended sign mode status register Stat bit 0 toAssembly Language Instructions 181 RXM Vcall Vectored Call Push PC + 0x7F00R7 R7 + Flags Affected See Also RET, IRET, CALL, C cc Example 14.85 XOR Logical XOR XOR src For two operandsXOR src For three operands TAG bit is set accordingly Src is flagadrs Example 4.14.85.2 XOR A0, A0, 2, ++A XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsExample 4.14.85.1 XOR A1, A1, 0x13FF XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Assembly Language Instructions 185Xorb Logical XOR Byte Xors Logical XOR String Dest stringXOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors A2, A2~, A2 14.88 ZAC Zero Accumulator PC PC + Flags Affected ZF =Zacs ZAC A1~, ++A Reset the content of offset accumulator string A1~ to zero Zacs Zero Accumulator StringZero the specified accumulator string ZAC Instruction Set Encoding Assembly Language Instructions 189Instruction Set Encoding 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 Assembly Language Instructions 195 196 Assembly Language Instructions 197 Description True condition Not true condition Instruction Set Summary Pma16 , Rmod Assembly Language Instructions 199 An~, An~ , next aAn~, pma16 An, An~ Adrs, a n~ , next a ~, adrs , next aAn ~, imm16 , next a MR , imm16 , next a Assembly Language Instructions 201 Adrs, TOSSTR, adrs Flagadrs† , TFn ~ , next a ~, a n~ , next a~ , a n~ Adrs An ~, An ~, imm16 , next a ~, a n~, a n , next a An~, An~ , next a NR+3 Assembly Language Instructions 203 TFn, flagadrs NR+3 TFn, cc , RxAn~, An~, pma16 An~, An~, An ~, a n~ ~, a n, a n~ , next a~, a n, a n~ ~, a n~, PH Conditional on RCF=1 Not condition RCF=0 Conditional on RZF=0 and RCF=1 Not condition RZF≠ 0 or RCF≠Conditional on RZF=1 Not condition RZF=0 Conditional on ZF=0 and SF=1 Not condition ZF≠ Or SF≠ 206Assembly Language Instructions Instruction Set Summay MC = Pllm value+1 ⋅ 131.07 kHz 208Assembly Language Instructions Summay Language Instructions209 Instruction Set Summay 210Assembly Language Instructions Code Development Tools Introduction Pin IDC Connector top view looking at the board Code Development Tools MSP50C6xx Development Tools Guidelines Categories of MSP50Cxx Development ToolsSDK50P614 kit of 15 MSP50P614s MSP50C6xx Development Tools Guidelines Tools Definitions SPEECH-EVM†PC50C604† MSP50C6xx Development Tools Guidelines Software Tools-Definitions System Requirements MSP50C6xx Code Development ToolsDocumentation Hardware Tools Setup Red MSPSCANPORTI/F power Yellow Green Target board power Assembler Assembler DirectivesExamples Assembler An assembly language program #ELSE see #IF and #IFDEF #IF expression Do something here #ELSEDo other things here #ENDIF Example #IFDEF symbol #IFNDEF symbol Assembler Compiler CompilerForeword Type Name Mnemonic Range Size in Bytes Example Variable TypesExternal References Defines a replacement string for a given string DirectivesWithout Arguments With Arguments Include Files See #if directive #define STRLENGTHi Major Differences between C and C Function Prototypes and Declarations InitializationsRAM Usage Initialization values are stored in program memory Operator can take the following values predefined constants String FunctionsString Functions Constant Functions An example of the use of xferconst is Implementation Details ComparisonsThis section is C- specific Signed comparison of a and b. a is in A0, b is in A0~ Assembly Vector Unsigned comparison of a and b. a is in A0, b is in A0~Ult Ugt Division Function CallsStack frame has the following structure Low Address High Address Programming Example Cmmfunc bidonint i1,char *i2 is valid, butOn Call On RET #include cmmmacr.h Programming Example, C -- With Assembly Routines Reserved Implementation Details R7Param Addb R7,2 To C function return in roncoreturn OldR5 Return Addr Param R7,R5 Stack data Param R7,R5 Stack data Before call Parameter Return Addr Param Stack data Efficiency EfficiencyTo ASM function return Efficiency Real Time Clock Example Example 5-1. First Project Jrtc.rpj Hmodules Allocated by changing MAINRAM.IRX Efficiency CMM1.ASM Sixth file, cmm1ram.asm, allocates memory for cmm1.asm Allocated as follows MAIN.CMM Example 5-2. Second Project C-- With Speech Celp Celp.irx Util.objDspvar.irx dsputil.asm getbits.asm speak.asm speak.irx Isr Tim2isr.asm dacisr.asm J tim1isr.asm Tens.qfm MelpAmpm.qfm Dsp Ramendcustomer Ramstartcustomer Clock will need to say Assembly routines that will be called are declared externalNew C-- callable functions were declared global Cmmfunc speakHours Example 5-3. Third Project C-- with an LCD Celp Ampm.qfm Days.qfm Ones.qfm Teens.qfm Melp.irx Melp.objLcd Lcd.asm Lcd.irx External lcdsetio external lcdinit Case Efficiency Beware of Stack Corruption Beware of Stack Corruption Reported Bugs With Code Development Tool Reported Bugs With Code Development Tool Applications Application Circuits Application Circuits ∝ F 22 pF MSP50P614 only 100 kΩ3300 pF Applications6-3 Initializing the MSP50C6xx Initializing the MSP50C6xx File init.asm Applications6-5 JNZ Itsacpart Itsappart Applications6-7 TI-TALKS Example Code TI-TALKS Example CodeGetting Started RAM Overlay Creating a New ProjectRAM Overlay Applications6-9 RAM Overlay Adding Customer Variables Common Problems Page Customer Information Package Information Mechanical InformationDie Bond-Out Coordinates Signal and Pad Descriptions for the MSP50C614 Customer Information Signal and Pad Descriptions for the MSP50C605 Signal and Pad Descriptions for the MSP50C601 Signal and Pad Descriptions for the MSP50C604 Pin QFP Mechanical Information 13 NOM 13 12 11 10 9 8 7 6 5 4 3 2 Extra pin 3 4 5 6 7 8 9 10 11 12 13 Bottom View Bottom View of 120-Pin PGA Package of the MSP50P614 Bottom view 0x0006 Device number 0x0614 Customer Information Fields in the ROMCustomer Information Fields in the ROM Speech Specification Speech Development CycleDevice Production Sequence Software Design Hardware Design Device Production Sequence Ordering Information New Product Release Forms Nprf6xx Code Letter PJM Loopin 100-Pin QFP New Product Release Forms Nprf Approval of Prototypes and Authorization to Start Production NEW Product Release Form for MSP50C604 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C605 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C601 Option Selection New Product Release Forms Nprf Additional Information Topic Additional Information Additional Information