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Texas Instruments MSP50C6xx Bottom View of 120-Pin PGA Package of the MSP50P614, Bottom view

Models: MSP50C6xx

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Mechanical Information

Figure 7–4. Bottom View of 120-Pin PGA Package of the MSP50P614

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†It is important to provide a separate decoupling capacitor for the VDD, VSS pair which services the DAC. These pins are PGA numbers N3 and L4, respectively. The relatively high current demands of the digital-to-analog circuitry make this a requirement. Refer to section 6.1 for details.

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Texas Instruments MSP50C6xx manual Bottom View of 120-Pin PGA Package of the MSP50P614, Bottom view

Contents

MSP50C6xx Mixed-Signal Processor User’s Guide Important Notice How to Use This Manual About This ManualNotational Conventions IiiCsr -a /user/ti/simuboard/utilities Here is a sample program listingNotational Conventions Information About Cautions and Warnings TrademarksThis book may contain cautions and warnings Information About Cautions and WarningsPage Contents Contents Assembly Language InstructionsPeripheral Functions Contentsix Code Development ToolsApplications Customer InformationContentsxi PLL Performance -27 2-10 Instruction Execution and TimingTables Contentsxiii TablesXiv Introduction to the MSP50C6xx Features of the MSP50C6xx Features of the MSP50C6xxApplications Consumer EducationIndustrial Aids for the HandicappedDevelopment Device MSP50P614 Development Device MSP50P614Functional Description for the MSP50C614 Functional Description for the MSP50C614Functional Description for the MSP50C614 Crystal Reference Oscillator Connections Resistor Trim Oscillator ConnectionsReset Circuit MSP50C601, MSP50C604, and MSP50C605 MSP50C601, MSP50C604, and MSP50C605Page MSP50C6xx Architecture Architecture Overview MSP50C6xx Core Processor Block Diagram MSP50C6xx ArchitectureComputational Unit Block Diagram Computation Unit MultiplierSigned and Unsigned Integer Representation Computation UnitComputation Unit Overview of the Multiplier Unit Operation Arithmetic Logic UnitAccumulator Block Overview of the Arithmetic Logic Unit Points to AC Register #Points to Offset Data Memory Address Unit Data Memory Address UnitRAM Configuration Data Memory Address UnitData Memory Addressing Modes Bit Logic Unit Program Counter UnitProgram Counter Unit Memory Map Memory Organization RAM and ROMMemory Organization RAM and ROM C6xx Memory Map not drawn to scale Peripheral Communications PortsReset LOW Summary of MSP50C614’s Peripheral Communications PortsInterrupt Vectors Summary of C614’s Peripheral Communications PortsInterrupt Name ROM address Event Source Interrupt Priority ROM Code Security Block Protection Word Address 0x7FFEWrite only True Protection Marker N TM= the value programmed at TM5 … TM0 true Protection marker≡ the binary complement of N TM = the value programmed at FM5 … FM0 falseMacro Call Vectors Interrupt LogicInterrupt Logic Bit wide location 00 ← INT number IFRInterrupt Logic Interrupt Initialization Sequence Clock Control Oscillator OptionsPLL Performance Clock ControlPLL Performance Clock Speed Control Register Clock frequency kHz = Pllm register value + 1 ⋅ 65.536 kHzRTO Oscillator Trim Adjustment ClkSpdCtrl registerRtrim Register Read Only Applies to MSP50C6xx Device Only ClkSpdCtrl Value Copied ShadedTimer Registers Timer RegistersTimer Registers Reduced Power Modes Reduced Power ModesReduced Power Modes Reduced Power Modes Programmable Bits Needed to Control Reduced Power Modes Component Determined Deeper sleep … relatively less power →By Controls Deeper sleep … Event DeterminedGlobal interrupt enable is SET Execution Timing Execution TimingPeripheral Functions I/O General-Purpose I/O PortsMSP50C614 MSP50C604 MSP50C6050x14h 0x1Ch 0x24h Possible control values = High-Z Input Control register address 0x04h†Peripheral Functions Dedicated Input Port F Input Port F Dedicated Output Port GData register address Branch on D Port Totem-Pole Output Port GInternal and External Interrupts Summary of the interrupts is given in Table InterruptsInterrupt Vector Source Trigger Event Priority Comment Digital-to-Analog Converter DAC Pulse-Density Modulation RateDAC Control and Data Registers Digital-to-Analog Converter DACOverflow bits Least-significant data value Ignored bits PDM Clock Divider PDM Clock DividerDigital-to-Analog Converter DAC Example 3-1 -kHz Sampling Rate DACExample 3-2 -kHz Sampling Rate Comparator INT6 INT7 TIMER1 Enable Comparator Interrupt/General Control Register Interrupt/General Control RegisterIntGenCtrl register Address Bit wide location LowInterrupt/General Control Register Hardware Initialization States Hardware Initialization StatesHardware Initialization States Bit Bit Name Initialized Value Description Assembly Language Instructions Instruction Set SummaryIntroduction System RegistersAssembly Language Instructions Top of Stack, TOSSystem Registers PostdecrementProduct Low Register PL Product High Register PHAccumulators AC0-AC31 Accumulator Pointers AP0-AP3 Indirect Register R0-R7Bit Bits 16String Register STR Status Register StatStatus Register Stat FunctionInstruction Syntax and Addressing Modes 1 MSP50P614/MSP50C614 Instruction SyntaxAddressing Mode Encoding Addressing ModesBit Opcode Next aAddressing Mode Bits and adrs Field Description Rx Bit DescriptionMSP50P614/MSP50C614 Addressing Modes Summary Auto Increment and Auto Decrement ModesFlag addressing mode encoding, flagadrs Flag RepeatFlagadrs Clocks Words Addressing Operation, † SyntaxImmediate Addressing SyntaxExample ADD AP0, 0x1ADirect Addressing MOV *0x012F * 2, *A0Mulr *0x02A1 Memory OperandIndirect Addressing Indirect Addressing SyntaxSyntaxOperation Rx x = 0 Address Memory Operand ++  --  ++R5Relative Addressing MOV A2, *R0*R4++ Movb *R7++, A3Rx x = 0 Address Index Register R5 Operand A0, *R3+R5R6 page register Address Bit positive offset Operand MOV A3, *R6+0x10 Rx x = 0 Address Memory OperandFlag Addressing TF1, *0x20Or TF2, *R6+0x02 XOR TF1, *R6+0x208 Tag/Flag Bits Possible sources of confusion Consider the following code TF1,*ram1 TF1 bit in Stat is set!?10. Symbols and Explanation Symbol ExplanationInstruction Classification Instruction Classification11. Symbols and Explanation 11. Instruction ClassificationNext a Accumulator control bits as described in Table Class Sub- DescriptionClass Sub Description 12. Classes and Opcode Definition Class 1 Instructions Memory and Accumulator Reference13. Class 1 Instruction Encoding 14. Class 1a Instruction DescriptionC1a ~A~ C1b15. Class 1b Instruction Description C1b Mnemonic DescriptionClass 2 Instructions Accumulator and Constant Reference 17. Class 2a Instruction Description 16. Class 2 Instruction EncodingC2a Mnemonic Description 18. Class 2b Instruction Description Class 3 Instruction Accumulator ReferenceC2b Mnemonic Description ADD An ~, An ~, imm16 , next a19. Class 3 Instruction Encoding 20. Class 3 Instruction DescriptionMnemonic Description Subs An~, An~, An Modified ADD An~, An~, An , next aZero or be set equal to the sign bit Xsgm dependent SUB a n~, a n~, PH , next aALU status is modified. String bit causes subtract with Carry status CFPH msbs extended by XM mode bit. Transfer the lower MOV SV, An~ , next aIs modified From the offset accumulator A~=1 or accumulatorClass 4 Instructions Address Register and Memory Reference 21. Class 4a Instruction Encoding22. Class 4a Instruction Description 23. Class 4b Instruction Description24. Class 4c Instruction Description 25. Class 4d Instruction DescriptionClass 5 Instructions Memory Reference 26. Class 5 Instruction Encoding27. Class 5 Instruction Description Adrs. Transfer status is modifiedDressing mode adrs. Transfer status is modified MOV adrs, TOSStag adrs Tag bitClass 6 Instructions Port and Memory Reference 28. Class 6a Instruction Encoding29. Class 6a Instruction Description C6a Mnemonic DescriptionClass 7 Instructions Program Control 30. Class 6b Instruction DescriptionC6b Mnemonic Description 31. Class 7 Instruction Encoding and Description Vector8Jcc CccClass 8 Instructions Logic and Bit 32. Class 8a Instruction Encoding33. Class 8a Instruction Description 34. Class 8b Instruction DescriptionClass 9 Instructions Miscellaneous C8a Mnemonic Description35. Class 9a Instruction Encoding 36. Class 9a Instruction Description37. Class 9b Instruction Description C9a Mnemonic DescriptionBit, Byte, Word and String Addressing 38. Class 9c Instruction Description39. Class 9d Instruction Description C9c Mnemonic DescriptionGlobal Flags Relative 0000h 0001h 0002h 0040h 0041h Nnnn 17th BitWord 0000h MS Byte LS ByteMode Address Used Data Order Rx Post modify † 40. Data Memory Address and Data RelationshipMovb A0, *0x0003 MOV A0, *0x0004Which uses the absolute word memory address Rflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational ModesComputational Setting Resetting Function Mode Instruction 41. MSP50P614/MSP50C614 Computational ModesSXM Example 4.6.2 Sovm Example 4.6.1 SovmExample 4.6.1 SXM Hardware Loop Instructions Hardware Loop InstructionsSyntax Operation Limitations 42. Hardware Loops in MSP50P614/MSP50C614Completion of the BEGLOOP/ENDLOOP block String Instructions 43. Initial Processor State for String InstructionsData memory *address = data Program memory *address = dataMulapl A0, A0~ Lookup Instructions 44. Lookup InstructionsLookup Instructions Instructions Description Data TransferMOV An, adrs SUB An MOV An, *An Input/Output Instructions Special Filter InstructionsInput/Output Instructions Xk-2 Xk+2 Xk-1 xk+1 32 orSpecial Filter Instructions Special Filter Instructions STR,0 0x0100 0x0102 0x01040x0106 Go back N words to wrap aroundAfter FIR/COR execution Important Note About Setting the Stat Register Firkcoeffs Coeffarray address FIRK/CORK only Program memory FIRK/CORK Coeffarray Samplebuf addressFIR/COR only = 0..N CoeffarraySamplebuf Coeffarray is stored Conditionals ConditionalsSymbol Meaning OperandsOffset16 ≤ Port4 ≤ Port6 ≤Adrsn ClkDma n FlgPma n Offset nPort n 45. Auto Increment and Decrement 46. Addressing Mode Bits and adrs Field Description47. Flag Addressing Syntax and BIts Individual Instruction Descriptions Individual Instruction Descriptions14.1 ADD Add word ExecutionDescription See AlsoPC PC + Flags Affected AddbOpcode Adds Add String Clock , clk Words , wAdds A1, A1~, A1 14.4 Bitwise A3, *R4 ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XorsTF2, *0x0020 Andb Bitwise and Byte Src byte PC PC +OF, SF, ZF, CF are set accordingly Clock , clk Word , wAnds A0, A0~, A0 Ands Bitwise and StringAnds A0, A0~, *R2 Begloop Begin Loop Save next instruction address PC +Flags Affected None Opcode Order to loop N timesCall Unconditional Subroutine Call RET TOS 14.9 CccNOP 48. Names for cc True condition Not true conditionSyntax Alternate Syntax Description CALL, VCALL, RET, Iret 0x2010CTF1 Crnbe14.10 CMP Compare Two Words Stat flags set by src src1 operationPC = PC + w CMPB, CMPS, Jcc, CccCMP R2, 0xfe20 CMP R0, R5Cmpb Compare Two Bytes Cmpb R3Cmps Compare Two Strings PC PC + w Flags AffectedCmps A1~ Cmps A2, A2~With RPT instruction. See .11 for more detail on the setup 14.13 COR Correlation Filter FunctionAn, *Rx 3nR+2 Rxeven = Rxeven + R5Cork Correlation Filter Function Sample data. During Cork execution, interrupt is queued3n R+2 Xeven = R xeven + R5Endloop End Loop Decrement R4 by n 1 or PC first address after Begloop elseArgument, it assumes n =1 BEGLOOP, InteExtsgn Sign Extend Word ~ , next aCopy accumulator sign flag SF to all 16 bits of a n ~ Dest , modExtsgns Sign Extend String An~100 Assembly Language Instructions 101 14.18 FIR FIR Filter Function Coefficients in RAMAn, *Rx 2nR+2 Rxeven++102 Assembly Language Instructions 103 FirkIdle Halt Processor 104INS, OUT, Outs 14.21 Input From Port Into WordA2~, 0x3d 14.22 INS Input From Port Into String IN, OUT, OutsIntd Interrupt Disable Assembly Language Instructions 107STAT.IM IM is Stat bit PC PC + Flags Affected None OpcodeInterrupt Enable InteINTD, Iret Clock, clk Word, w With RPT, clk ClassAssembly Language Instructions 109 Iret Return From InterruptConditional Jumps RCF and RZF affected by post-modification of RAssembly Language Instructions 111 Cc namesIf test condition is false, a NOP is executed See Also JMP, CALL, C cc Example JNZJE 0x2010, R3++R5 Jtag 0x2010, R2++14.27 JMP Unconditional Jump Post-modify R x if specifiedSee Also Cc, CALL, C cc Example Instruction Operation14.28 MOV Move Data Word From Source to Destination XSF, XZF are set accordingly Clock , clk Word , w With RPT , clk ClassTF n, cc , R STR, imm8Assembly Language Instructions 117 MOV adrs, DPWith some operand types MOVU, MOVT, MOVB, MOVBS, Movs Example 4.14.28.10 MOV MR, A3, --AExample 4.14.28.11 MOV A1~, *A1 Example 4.14.28.12 MOV *0x0200 * 2, R0Example 4.14.28.13 MOV R1, 0x0200 Example 4.14.28.15 MOV *0x0200 * 2, R0Transfer R5 to R0 Example Example 4.14.28.18 MOV *R6 + 8 * 2, DPExecution An + PH Movaph Move With Adding PHMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs Movaphs Move With Adding PH Execution + PHBackground. See .8 for more details MOVAPH, MOVTPH, MOVTPHS, MOVSPH, MovsphsMovb Move Byte From Source to Destination Copy value of unsigned src byte to dest byteMovb A0, *R2 Copy data memory byte pointed by R2 to accumulator A0Movb A0, 0xf2 Movb *R2, A0Movb R2 Movbs Move Byte String from Source to Destination TAG bit is set to bit 17th valueMovbs A2, *0x0200 Movbs *0x0200, A2Movs Move String from Source to Destination An ~ , adrsAdrs , An ~ Adrs , *AnMOVU, MOV, MOVT, MOVB, Movbs Movs A2~Movs A1, A1~ Movs A1~, A1MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs Movsph128 An second word PH MR contents of adrs Assembly Language Instructions 129Movsphs Move String With Subtract From PH DetailsMovt PC PC + w Flags Affected None OpcodeAvailable MOVU, MOV, MOVT, MOVB, MOVBS, MovsMovu Move Data Unsigned TAG bit is set accordingly UM is set toMOV, MOVB, MOVT, MOVBS, Movs Copy the value pointed by R3 to MRXxxxxx Xxxx00 Flag Bit MR/SV An S APn132 14.38 MUL Multiply Rounded MR * src PC PC + w Flags AffectedAccumulator pointer if specified MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, MulaplMulr Multiply Rounded With No Data Transfer MR * src PC PC + Flags AffectedMULS, MUL, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls MulaplLength nS+2, where nS is the value in STR register Assembly Language Instructions 135Muls Multiply String With No Data Transfer PH,PL MR * src stringMulapl Multiply and Accumulate Result PH ,PL MR * srcBackground. See .8 for more detail MULAPLS, MULSPL, MULSPLS, MULTPL, MultplsMR * src Mulapls Multiply String and Accumulate ResultMULAPL, MULSPL, MULSPLS, MULTPL, Multpls Mulspl Multiply and Subtract PL From Accumulator Occuring in the background. See .8 for more detailsMULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspl adrsMulspls Multiply String and Subtract PL From Accumulator From dest stringMULSPL, MULTPL, MULTPLS, MULAPL, Mulapls Syntax Description Mulspls adrsMultpl Multiply and Transfer PL to Accumulator ~ , a n ~ , next aValue of src. The 16 MSBs Multiply MR by data memory word, move PL to a nMultpls Execution PH, PL MR * src PC PC + Flags AffectedMULTPL, MULAPL, MULAPLS, MULSPL, Mulspls Example 4.14.46.2 Multpls A2, A2~Negac Two’s Complement Negation of Accumulator AccumulatorNEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Example 4.14.47.1 Negac A3~, A3, --AAssembly Language Instructions 143 Negacs Two’s Complement Negation of Accumulator StringDest accumulator string NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, NotacsExecution PC PC + 14.49 NOP No OperationRPT Notac One’s Complement Negation of Accumulator NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, XorsNEGAC, Negacs Example 4.14.50.1 Notac A3~, A3, --ANotacs One’s Complement Negation of Accumulator String Accumulator stringNegacs A3~TFn bits in Stat register are set accordingly 14.52 or Bitwise Logical orAccumulator pointers are allowed with some operand types ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs Or A0, *R0++R5Or TF1, *R6+0x22 14814.53 ORB Bitwise or Byte Or srcAccumulator is affected OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs14.54 ORS Bitwise or String PC + w Flags AffectedOR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs ORS A0, A0~, A0Address is multipled by 4 to get the actual port address 14.55 OUTOUTS, IN, INS Outs Output String to Port Port6 specified in the instructionOUT, IN, INS Port6 , An ~14.57 RET Return From Subroutine CALL, Ccc PC TOSR7 R7 Flags Affected CALL, i.e., RET followed by a RET should not be allowedSflag , Stag , Rtag Rflag Reset Memory FlagExample 4.14.58.2 Rflag *R6 + Reset Fractional Mode Syntax Resets the fractional mode. Clears FM bit of Stat14.59 RFM STAT.FMRovm Reset Overflow Mode Saturation output normal modeResets the overflow mode to zero Stat .OM14.61 RPT Repeat Next Instruction If RPT adrs8 Load src to repeat counterLoad imm8 to repeat counter After execution completesRtag Reset Tag Stag , Rflag , SflagRtag *R6+0x0002 Rtag *R6+0x000314.63 RXM Reset Extended Sign Mode Assembly Language Instructions 159STAT.XM SXMAddress flagadrs only accesses the 17 th bit Sflag Set Memory FlagRflag , Stag , Rtag 16014.65 SFM Set Fractional Mode Mode for signed fractional arithmeticAssembly Language Instructions 161 Set fractional mode. Set FM bit of Stat to14.66 SHL Shift Left PH , PLAccumulator. Use Shlac for this purpose ShlsShlac Shift Left Accumulator Its offset. LSB of result is set to zeroShift accumulator A1 by one bit to the left Example 4.14.67.2 Shlac A1~, A1, --AAccumulators in the string Shlacs Shift Left Accumulator String Individually164 Shlapl Shift Left with Accumulate Example 4.14.69.1 Shlapl A0, *R4++R5Shlapl A2, *R1++ Example 4.14.69.3 Shlapl A1, A1, ++AShift data memory string left, add PL to a n Shlapls Shift Left String With AccumulateShift a n ~ string left, addb PL to a n ~ Assembly Language Instructions 167 Shls Shift Left Accumulator String to ProductExecution PH, PL An~Shlspl Shift Left With Subtract PL Example 4.14.72.1 Shlspl A0, *R4++R5Shlspl A2, *R1++ Example 4.14.72.3 Shlspl A1, A1, ++AAssembly Language Instructions 169 Shlspls Shift Left String With Subtract PLNS+3 NR+3 Shift RAM string left, subtract PL from AnShltpl Shift Left and Transfer PL to Accumulator Example 4.14.74.1 Shltpl A0, *R4++R5Shltpl A2, *R1++ Example 4.14.74.3 Shltpl A1, A1, ++AShltpls Shift Left String and Transfer PL to Accumulator Receives the same data as PHSHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls Shift the accumulator string A1 by nSV bits to the leftShrac Shift Accumulator Right RegisterShift right one bit the accumulator A1 Example 4.14.76.2 Shrac A1~, A1, ++AAssembly Language Instructions 173 Shracs Shift Accumulator String RightSHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl ShltplsSet Overflow Mode Syntax Output DSP modeSovm STAT.OMRTAG, RFLAG, Sflag StagStag *0x401 14.80 SUB Subtract Dest, src , src1 , next aAn ~ , An , adrs , next a An ~ , An ~ , imm16 , next aExample 4.14.80.2 SUB A0, A0, 2, ++A SUB A1, A1~, A1SUB A3~, A3, *R4 SUB R3, R5Subb Subtract Byte Subtract 0x45 from accumulator A2 byteSubtract 0xF2 from register R3 byte Syntax Description Subb a n, imm8Subs Subtract Accumulataor String Assembly Language Instructions 179NR+2 Subs A2, A2, A2~ Subs A2, A2~, A2Subs A3~, A3~, PH 18014.83 SXM Set Extended Sign Mode Sets extended sign mode status register Stat bit 0 toAssembly Language Instructions 181 RXMVcall Vectored Call Push PC + 0x7F00R7 R7 + Flags Affected See Also RET, IRET, CALL, C cc Example14.85 XOR Logical XOR XOR src For two operandsXOR src For three operands TAG bit is set accordingly Src is flagadrsExample 4.14.85.1 XOR A1, A1, 0x13FF XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsExample 4.14.85.2 XOR A0, A0, 2, ++A Xorb Logical XOR Byte Assembly Language Instructions 185XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors Logical XOR String Dest stringXOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors A2, A2~, A214.88 ZAC Zero Accumulator PC PC + Flags Affected ZF =Zacs ZAC A1~, ++AReset the content of offset accumulator string A1~ to zero Zacs Zero Accumulator StringZero the specified accumulator string ZACInstruction Set Encoding Assembly Language Instructions 189Instruction Set Encoding 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 Assembly Language Instructions 195 196 Assembly Language Instructions 197 Description True condition Not true conditionInstruction Set Summary Pma16 , Rmod Assembly Language Instructions 199 An~, An~ , next aAn~, pma16 An, An~Adrs, a n~ , next a ~, adrs , next aAn ~, imm16 , next a MR , imm16 , next aAssembly Language Instructions 201 Adrs, TOSSTR, adrs Flagadrs† , TFn~ , next a ~, a n~ , next a~ , a n~ Adrs An ~, An ~, imm16 , next a ~, a n~, a n , next aAn~, An~ , next a NR+3 Assembly Language Instructions 203 TFn, flagadrs NR+3 TFn, cc , RxAn~, An~, pma16 An~, An~, An~, a n~ ~, a n, a n~ , next a~, a n, a n~ ~, a n~, PHConditional on RCF=1 Not condition RCF=0 Conditional on RZF=0 and RCF=1 Not condition RZF≠ 0 or RCF≠Conditional on RZF=1 Not condition RZF=0 Conditional on ZF=0 and SF=1 Not condition ZF≠ Or SF≠206Assembly Language Instructions Instruction Set SummayMC = Pllm value+1 ⋅ 131.07 kHz 208Assembly Language Instructions 209 Language InstructionsSummay Instruction Set Summay 210Assembly Language Instructions Code Development Tools Introduction Pin IDC Connector top view looking at the board Code Development ToolsMSP50C6xx Development Tools Guidelines Categories of MSP50Cxx Development ToolsSDK50P614 kit of 15 MSP50P614s MSP50C6xx Development Tools GuidelinesTools Definitions SPEECH-EVM†PC50C604†MSP50C6xx Development Tools Guidelines Software Tools-Definitions Documentation MSP50C6xx Code Development ToolsSystem Requirements Hardware Tools Setup Red MSPSCANPORTI/F power Yellow Green Target board powerAssembler Assembler DirectivesExamples AssemblerAn assembly language program #ELSE see #IF and #IFDEF#IF expression Do something here #ELSEDo other things here #ENDIFExample #IFDEF symbol #IFNDEF symbolAssembler Foreword CompilerCompiler External References Variable TypesType Name Mnemonic Range Size in Bytes Example Defines a replacement string for a given string DirectivesWithout Arguments With ArgumentsInclude Files See #if directive#define STRLENGTHi Major Differences between C and C Function Prototypes and Declarations InitializationsRAM Usage Initialization values are stored in program memoryString Functions String FunctionsOperator can take the following values predefined constants Constant Functions An example of the use of xferconst isImplementation Details ComparisonsThis section is C- specific Signed comparison of a and b. a is in A0, b is in A0~Assembly Vector Unsigned comparison of a and b. a is in A0, b is in A0~Ult UgtDivision Function CallsStack frame has the following structure Low Address High AddressProgramming Example Cmmfunc bidonint i1,char *i2 is valid, butOn Call On RET#include cmmmacr.h Programming Example, C -- With Assembly Routines ReservedImplementation Details R7Param Addb R7,2 To C function return in roncoreturn OldR5 Return Addr Param R7,R5 Stack data Param R7,R5 Stack data Before call Parameter Return Addr Param Stack data To ASM function return EfficiencyEfficiency Efficiency Real Time Clock Example Example 5-1. First ProjectJrtc.rpj Hmodules Allocated by changing MAINRAM.IRXEfficiency CMM1.ASM Sixth file, cmm1ram.asm, allocates memory for cmm1.asm Allocated as followsMAIN.CMM Example 5-2. Second Project C-- With Speech Celp Celp.irx Util.objDspvar.irx dsputil.asm getbits.asm speak.asm speak.irx Isr Tim2isr.asm dacisr.asm J tim1isr.asmTens.qfm MelpAmpm.qfm DspRamendcustomer Ramstartcustomer New C-- callable functions were declared global Assembly routines that will be called are declared externalClock will need to say Cmmfunc speakHours Example 5-3. Third Project C-- with an LCD Lcd Lcd.asm Lcd.irx Melp.irx Melp.objCelp Ampm.qfm Days.qfm Ones.qfm Teens.qfm External lcdsetio external lcdinit Case Efficiency Beware of Stack Corruption Beware of Stack CorruptionReported Bugs With Code Development Tool Reported Bugs With Code Development ToolApplications Application Circuits Application Circuits∝ F 22 pF MSP50P614 only 100 kΩ3300 pF Applications6-3Initializing the MSP50C6xx Initializing the MSP50C6xxFile init.asm Applications6-5JNZ Itsacpart Itsappart Applications6-7 Getting Started TI-TALKS Example CodeTI-TALKS Example Code RAM Overlay Creating a New ProjectRAM Overlay Applications6-9RAM Overlay Adding Customer VariablesCommon Problems Page Customer Information Die Bond-Out Coordinates Mechanical InformationPackage Information Signal and Pad Descriptions for the MSP50C614 Customer InformationSignal and Pad Descriptions for the MSP50C605 Signal and Pad Descriptions for the MSP50C601 Signal and Pad Descriptions for the MSP50C604 Pin QFP Mechanical Information 13 NOM 13 12 11 10 9 8 7 6 5 4 3 2 Extra pin 3 4 5 6 7 8 9 10 11 12 13 Bottom ViewBottom View of 120-Pin PGA Package of the MSP50P614 Bottom viewCustomer Information Fields in the ROM Customer Information Fields in the ROM0x0006 Device number 0x0614 Speech Specification Speech Development CycleDevice Production Sequence Software Design Hardware DesignDevice Production Sequence Ordering Information New Product Release Forms Nprf6xx Code Letter PJM Loopin 100-Pin QFPNew Product Release Forms Nprf Approval of Prototypes and Authorization to Start Production NEW Product Release Form for MSP50C604 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C605 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C601 Option Selection New Product Release Forms Nprf Additional Information TopicAdditional Information Additional Information