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Texas Instruments MSP50C6xx manual Assembly Language Instructions 117, MOV adrs, DP

Models: MSP50C6xx

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Instructions	16	15	14	13	12	11	10	9		8	7	6	5	4		3	2		1	0

MOV Rx, R5	1	1	1	1	1	1	1	0		0	1	1	0			Rx			0	0

MOV SV, imm4	1	1	1	1	1	1	0	1		0	0	0	0	0			imm4

MOV SV, {adrs}4	1	1	0	1	1	0	0	0		0					adrs
	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV PH, {adrs}	1	1	0	1	1	0	0	0		1					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV MR, {adrs}	1	1	0	1	1	1	0	0		0					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV APn, {adrs}	1	1	0	1	1	0	1	APn							adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV STAT, {adrs}	1	1	0	1	1	1	1	1		1					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV TOS, {adrs}	1	1	0	1	1	0	0	1		0					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV {adrs}, PH	1	1	0	1	0	0	0	0		1					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV {adrs}, MR	1	1	0	1	0	1	0	0		0					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV {adrs}, STAT	1	1	0	1	0	0	0	1		0					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV {adrs}, STR	1	1	0	1	0	0	0	1		1					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV {adrs}, DP	1	1	0	1	0	1	0	1		0					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV {adrs}, SV	1	1	0	1	0	0	0	0		0					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV {adrs}, APn	1	1	0	1	0	0	1	An							adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV {adrs}, TOS	1	1	0	1	0	1	0	1		1					adrs

	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV STR, {adrs}8	1	1	0	1	1	0	0	1		1					adrs
	x			dma16 (for direct) or offset16 (long relative) [see section 4.13]

MOV {flagadrs}, TFn	1	0	0	1	1	flg	Not	0		0	1				flagadrs

MOV TFn, {flagadrs}	1	0	0	1	1	flg	Not	0		0	0				flagadrs

MOV TFn, {cc} [, Rx]	1	0	0	1	0	flg	Not				cc					Rx			0	0

MOV STR, imm8	1	1	1	1	1	1	0	0		1					imm8

MOV APn, imm5	1	1	1	1	1	0	1	An			0	0	0				imm5

Assembly Language Instructions

4-117

Image 203

Texas Instruments MSP50C6xx manual Assembly Language Instructions 117, MOV adrs, DP

Contents

MSP50C6xx Mixed-Signal Processor User’s Guide Important Notice Iii How to Use This ManualAbout This Manual Notational ConventionsNotational Conventions Here is a sample program listingCsr -a /user/ti/simuboard/utilities Information About Cautions and Warnings Information About Cautions and WarningsTrademarks This book may contain cautions and warningsPage Contents Peripheral Functions Assembly Language InstructionsContents Code Development Tools ContentsixCustomer Information ApplicationsPLL Performance -27 2-10 Instruction Execution and Timing ContentsxiTables Tables ContentsxiiiXiv Introduction to the MSP50C6xx Features of the MSP50C6xx Features of the MSP50C6xxAids for the Handicapped ApplicationsConsumer Education IndustrialDevelopment Device MSP50P614 Development Device MSP50P614Functional Description for the MSP50C614 Functional Description for the MSP50C614Functional Description for the MSP50C614 Resistor Trim Oscillator Connections Crystal Reference Oscillator ConnectionsReset Circuit MSP50C601, MSP50C604, and MSP50C605 MSP50C601, MSP50C604, and MSP50C605Page MSP50C6xx Architecture Architecture Overview MSP50C6xx Architecture MSP50C6xx Core Processor Block DiagramComputational Unit Block Diagram Computation Unit Computation UnitMultiplier Signed and Unsigned Integer RepresentationComputation Unit Arithmetic Logic Unit Overview of the Multiplier Unit OperationAccumulator Block Overview of the Arithmetic Logic Unit Points to Offset AC Register #Points to Data Memory Address Unit Data Memory Address UnitData Memory Address Unit RAM ConfigurationData Memory Addressing Modes Program Counter Unit Program Counter UnitBit Logic Unit Memory Organization RAM and ROM Memory Organization RAM and ROMMemory Map Peripheral Communications Ports C6xx Memory Map not drawn to scaleSummary of MSP50C614’s Peripheral Communications Ports Reset LOWInterrupt Name ROM address Event Source Interrupt Priority Summary of C614’s Peripheral Communications PortsInterrupt Vectors ROM Code Security True Protection Marker N TM Block Protection WordAddress 0x7FFE Write only= the value programmed at FM5 … FM0 false = the value programmed at TM5 … TM0 trueProtection marker ≡ the binary complement of N TMInterrupt Logic Interrupt LogicMacro Call Vectors IFR Bit wide location 00 ← INT numberInterrupt Logic Interrupt Initialization Sequence Clock Control Clock ControlOscillator Options PLL PerformancePLL Performance Clock frequency kHz = Pllm register value + 1 ⋅ 65.536 kHz Clock Speed Control RegisterClkSpdCtrl register RTO Oscillator Trim AdjustmentClkSpdCtrl Value Copied Shaded Rtrim Register Read Only Applies to MSP50C6xx Device OnlyTimer Registers Timer RegistersTimer Registers Reduced Power Modes Reduced Power ModesReduced Power Modes Reduced Power Modes Programmable Bits Needed to Control Reduced Power Modes By Controls Deeper sleep … relatively less power →Component Determined Event Determined Deeper sleep …Global interrupt enable is SET Execution Timing Execution TimingPeripheral Functions MSP50C604 MSP50C605 I/OGeneral-Purpose I/O Ports MSP50C614Peripheral Functions Control register address 0x04h†0x14h 0x1Ch 0x24h Possible control values = High-Z Input Dedicated Input Port F Data register address Dedicated Output Port GInput Port F Totem-Pole Output Port G Branch on D PortInternal and External Interrupts Interrupt Vector Source Trigger Event Priority Comment InterruptsSummary of the interrupts is given in Table Digital-to-Analog Converter DAC Digital-to-Analog Converter DACPulse-Density Modulation Rate DAC Control and Data RegistersOverflow bits Least-significant data value Ignored bits PDM Clock Divider PDM Clock DividerDigital-to-Analog Converter DAC DAC Example 3-1 -kHz Sampling RateExample 3-2 -kHz Sampling Rate Comparator INT6 INT7 TIMER1 Enable Comparator Address Bit wide location Low Interrupt/General Control RegisterInterrupt/General Control Register IntGenCtrl registerInterrupt/General Control Register Hardware Initialization States Hardware Initialization StatesHardware Initialization States Bit Bit Name Initialized Value Description Instruction Set Summary Assembly Language InstructionsSystem Registers IntroductionPostdecrement Assembly Language InstructionsTop of Stack, TOS System RegistersAccumulators AC0-AC31 Product High Register PHProduct Low Register PL Bits 16 Accumulator Pointers AP0-AP3Indirect Register R0-R7 BitStatus Register Stat String Register STRFunction Status Register Stat1 MSP50P614/MSP50C614 Instruction Syntax Instruction Syntax and Addressing ModesNext a Addressing Mode EncodingAddressing Modes Bit OpcodeRx Bit Description Addressing Mode Bits and adrs Field DescriptionAuto Increment and Auto Decrement Modes MSP50P614/MSP50C614 Addressing Modes SummaryClocks Words Addressing Operation, † Syntax Flag addressing mode encoding, flagadrsFlag Repeat FlagadrsADD AP0, 0x1A Immediate AddressingSyntax ExampleMemory Operand Direct AddressingMOV *0x012F * 2, *A0 Mulr *0x02A1Rx x = 0 Address Memory Operand ++  --  ++R5 Indirect AddressingIndirect Addressing Syntax SyntaxOperationMovb *R7++, A3 Relative AddressingMOV A2, *R0 *R4++R6 page register Address Bit positive offset Operand A0, *R3+R5Rx x = 0 Address Index Register R5 Operand Rx x = 0 Address Memory Operand MOV A3, *R6+0x10XOR TF1, *R6+0x20 Flag AddressingTF1, *0x20 Or TF2, *R6+0x028 Tag/Flag Bits TF1,*ram1 TF1 bit in Stat is set!? Possible sources of confusion Consider the following codeInstruction Classification 10. Symbols and ExplanationSymbol Explanation Instruction ClassificationClass Sub- Description 11. Symbols and Explanation11. Instruction Classification Next a Accumulator control bits as described in TableClass Sub Description Class 1 Instructions Memory and Accumulator Reference 12. Classes and Opcode DefinitionC1b 13. Class 1 Instruction Encoding14. Class 1a Instruction Description C1a ~A~C1b Mnemonic Description 15. Class 1b Instruction DescriptionClass 2 Instructions Accumulator and Constant Reference C2a Mnemonic Description 16. Class 2 Instruction Encoding17. Class 2a Instruction Description ADD An ~, An ~, imm16 , next a 18. Class 2b Instruction DescriptionClass 3 Instruction Accumulator Reference C2b Mnemonic DescriptionSubs An~, An~, An Modified ADD An~, An~, An , next a 19. Class 3 Instruction Encoding20. Class 3 Instruction Description Mnemonic DescriptionCarry status CF Zero or be set equal to the sign bit Xsgm dependentSUB a n~, a n~, PH , next a ALU status is modified. String bit causes subtract withFrom the offset accumulator A~=1 or accumulator PH msbs extended by XM mode bit. Transfer the lowerMOV SV, An~ , next a Is modified21. Class 4a Instruction Encoding Class 4 Instructions Address Register and Memory Reference25. Class 4d Instruction Description 22. Class 4a Instruction Description23. Class 4b Instruction Description 24. Class 4c Instruction DescriptionAdrs. Transfer status is modified Class 5 Instructions Memory Reference26. Class 5 Instruction Encoding 27. Class 5 Instruction DescriptionTag bit Dressing mode adrs. Transfer status is modifiedMOV adrs, TOS Stag adrsC6a Mnemonic Description Class 6 Instructions Port and Memory Reference28. Class 6a Instruction Encoding 29. Class 6a Instruction DescriptionC6b Mnemonic Description 30. Class 6b Instruction DescriptionClass 7 Instructions Program Control Ccc 31. Class 7 Instruction Encoding and DescriptionVector8 Jcc32. Class 8a Instruction Encoding Class 8 Instructions Logic and BitC8a Mnemonic Description 33. Class 8a Instruction Description34. Class 8b Instruction Description Class 9 Instructions MiscellaneousC9a Mnemonic Description 35. Class 9a Instruction Encoding36. Class 9a Instruction Description 37. Class 9b Instruction DescriptionC9c Mnemonic Description Bit, Byte, Word and String Addressing38. Class 9c Instruction Description 39. Class 9d Instruction Description0000h MS Byte LS Byte Global Flags Relative0000h 0001h 0002h 0040h 0041h Nnnn 17th Bit WordMOV A0, *0x0004 Mode Address Used Data Order Rx Post modify †40. Data Memory Address and Data Relationship Movb A0, *0x0003Which uses the absolute word memory address Rflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational Modes41. MSP50P614/MSP50C614 Computational Modes Computational Setting Resetting Function Mode InstructionSXM Example 4.6.1 SXM Example 4.6.1 SovmExample 4.6.2 Sovm Hardware Loop Instructions Hardware Loop InstructionsCompletion of the BEGLOOP/ENDLOOP block 42. Hardware Loops in MSP50P614/MSP50C614Syntax Operation Limitations Program memory *address = data String Instructions43. Initial Processor State for String Instructions Data memory *address = dataMulapl A0, A0~ Instructions Description Data Transfer Lookup Instructions44. Lookup Instructions Lookup InstructionsMOV An, adrs SUB An MOV An, *An Xk-2 Xk+2 Xk-1 xk+1 32 or Input/Output InstructionsSpecial Filter Instructions Input/Output InstructionsSpecial Filter Instructions Special Filter Instructions STR,0 Go back N words to wrap around 0x0100 0x01020x0104 0x0106After FIR/COR execution Important Note About Setting the Stat Register Firkcoeffs Coeffarray Coeffarray address FIRK/CORK only Program memory FIRK/CORKCoeffarray Samplebuf address FIR/COR only = 0..NSamplebuf Coeffarray is stored Conditionals ConditionalsPort4 ≤ Port6 ≤ Symbol MeaningOperands Offset16 ≤Flg AdrsnClk Dma nPort n Offset nPma n 47. Flag Addressing Syntax and BIts 46. Addressing Mode Bits and adrs Field Description45. Auto Increment and Decrement Individual Instruction Descriptions Individual Instruction DescriptionsExecution 14.1 ADD Add wordSee Also DescriptionOpcode AddbPC PC + Flags Affected Clock , clk Words , w Adds Add StringAdds A1, A1~, A1 14.4 Bitwise TF2, *0x0020 ANDS, ANDB, OR, ORB, ORS, XOR, XORB, XorsA3, *R4 Clock , clk Word , w Andb Bitwise and ByteSrc byte PC PC + OF, SF, ZF, CF are set accordinglyAnds A0, A0~, *R2 Ands Bitwise and StringAnds A0, A0~, A0 Order to loop N times Begloop Begin LoopSave next instruction address PC + Flags Affected None OpcodeCall Unconditional Subroutine Call RET NOP 14.9 CccTOS True condition Not true condition 48. Names for ccSyntax Alternate Syntax Description Crnbe CALL, VCALL, RET, Iret0x2010 CTF1CMPB, CMPS, Jcc, Ccc 14.10 CMP Compare Two WordsStat flags set by src src1 operation PC = PC + wCMP R0, R5 CMP R2, 0xfe20Cmpb R3 Cmpb Compare Two BytesCmps A2, A2~ Cmps Compare Two StringsPC PC + w Flags Affected Cmps A1~Rxeven = Rxeven + R5 With RPT instruction. See .11 for more detail on the setup14.13 COR Correlation Filter Function An, *Rx 3nR+2Xeven = R xeven + R5 Cork Correlation Filter FunctionSample data. During Cork execution, interrupt is queued 3n R+2BEGLOOP, Inte Endloop End LoopDecrement R4 by n 1 or PC first address after Begloop else Argument, it assumes n =1Dest , mod Extsgn Sign Extend Word~ , next a Copy accumulator sign flag SF to all 16 bits of a n ~An~ Extsgns Sign Extend String100 Rxeven++ Assembly Language Instructions 10114.18 FIR FIR Filter Function Coefficients in RAM An, *Rx 2nR+2102 Firk Assembly Language Instructions 103104 Idle Halt ProcessorA2~, 0x3d 14.21 Input From Port Into WordINS, OUT, Outs IN, OUT, Outs 14.22 INS Input From Port Into StringIM is Stat bit PC PC + Flags Affected None Opcode Intd Interrupt DisableAssembly Language Instructions 107 STAT.IMClock, clk Word, w With RPT, clk Class Interrupt EnableInte INTD, IretIret Return From Interrupt Assembly Language Instructions 109RCF and RZF affected by post-modification of R Conditional JumpsCc names Assembly Language Instructions 111If test condition is false, a NOP is executed Jtag 0x2010, R2++ See Also JMP, CALL, C cc ExampleJNZ JE 0x2010, R3++R5Instruction Operation 14.27 JMP Unconditional JumpPost-modify R x if specified See Also Cc, CALL, C cc Example14.28 MOV Move Data Word From Source to Destination STR, imm8 XSF, XZF are set accordinglyClock , clk Word , w With RPT , clk Class TF n, cc , RMOV adrs, DP Assembly Language Instructions 117With some operand types Example 4.14.28.12 MOV *0x0200 * 2, R0 MOVU, MOVT, MOVB, MOVBS, MovsExample 4.14.28.10 MOV MR, A3, --A Example 4.14.28.11 MOV A1~, *A1Example 4.14.28.18 MOV *R6 + 8 * 2, DP Example 4.14.28.13 MOV R1, 0x0200Example 4.14.28.15 MOV *0x0200 * 2, R0 Transfer R5 to R0 ExampleMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs Movaph Move With Adding PHExecution An + PH MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs Movaphs Move With Adding PHExecution + PH Background. See .8 for more detailsCopy data memory byte pointed by R2 to accumulator A0 Movb Move Byte From Source to DestinationCopy value of unsigned src byte to dest byte Movb A0, *R2Movb R2 Movb *R2, A0Movb A0, 0xf2 Movbs *0x0200, A2 Movbs Move Byte String from Source to DestinationTAG bit is set to bit 17th value Movbs A2, *0x0200Adrs , *An Movs Move String from Source to DestinationAn ~ , adrs Adrs , An ~Movs A1~, A1 MOVU, MOV, MOVT, MOVB, MovbsMovs A2~ Movs A1, A1~128 MovsphMOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs Details An second word PH MR contents of adrsAssembly Language Instructions 129 Movsphs Move String With Subtract From PHMOVU, MOV, MOVT, MOVB, MOVBS, Movs MovtPC PC + w Flags Affected None Opcode AvailableCopy the value pointed by R3 to MR Movu Move Data UnsignedTAG bit is set accordingly UM is set to MOV, MOVB, MOVT, MOVBS, Movs132 MR/SV An S APnXxxxxx Xxxx00 Flag Bit MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl 14.38 MUL Multiply RoundedMR * src PC PC + w Flags Affected Accumulator pointer if specifiedMulapl Mulr Multiply Rounded With No Data TransferMR * src PC PC + Flags Affected MULS, MUL, MULAPL, MULSPL, MULSPLS, MULTPL, MultplsPH,PL MR * src string Length nS+2, where nS is the value in STR registerAssembly Language Instructions 135 Muls Multiply String With No Data TransferMULAPLS, MULSPL, MULSPLS, MULTPL, Multpls Mulapl Multiply and Accumulate ResultPH ,PL MR * src Background. See .8 for more detailMULAPL, MULSPL, MULSPLS, MULTPL, Multpls Mulapls Multiply String and Accumulate ResultMR * src Syntax Description Mulspl adrs Mulspl Multiply and Subtract PL From AccumulatorOccuring in the background. See .8 for more details MULSPLS, MULTPL, MULTPLS, MULAPL, MulaplsSyntax Description Mulspls adrs Mulspls Multiply String and Subtract PL From AccumulatorFrom dest string MULSPL, MULTPL, MULTPLS, MULAPL, MulaplsMultiply MR by data memory word, move PL to a n Multpl Multiply and Transfer PL to Accumulator~ , a n ~ , next a Value of src. The 16 MSBsExample 4.14.46.2 Multpls A2, A2~ MultplsExecution PH, PL MR * src PC PC + Flags Affected MULTPL, MULAPL, MULAPLS, MULSPL, MulsplsExample 4.14.47.1 Negac A3~, A3, --A Negac Two’s Complement Negation of AccumulatorAccumulator NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, NotacsNEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Assembly Language Instructions 143Negacs Two’s Complement Negation of Accumulator String Dest accumulator stringRPT 14.49 NOP No OperationExecution PC PC + Example 4.14.50.1 Notac A3~, A3, --A Notac One’s Complement Negation of AccumulatorNOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors NEGAC, NegacsA3~ Notacs One’s Complement Negation of Accumulator StringAccumulator string NegacsAccumulator pointers are allowed with some operand types 14.52 or Bitwise Logical orTFn bits in Stat register are set accordingly 148 ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOr A0, *R0++R5 Or TF1, *R6+0x22OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs 14.53 ORB Bitwise or ByteOr src Accumulator is affectedORS A0, A0~, A0 14.54 ORS Bitwise or StringPC + w Flags Affected OR, ORB, AND, ANDS, XOR, XORS, NOTAC, NotacsOUTS, IN, INS 14.55 OUTAddress is multipled by 4 to get the actual port address Port6 , An ~ Outs Output String to PortPort6 specified in the instruction OUT, IN, INSCALL, i.e., RET followed by a RET should not be allowed 14.57 RET Return From Subroutine CALL, CccPC TOS R7 R7 Flags AffectedExample 4.14.58.2 Rflag *R6 + Rflag Reset Memory FlagSflag , Stag , Rtag STAT.FM Reset Fractional Mode SyntaxResets the fractional mode. Clears FM bit of Stat 14.59 RFMStat .OM Rovm Reset Overflow ModeSaturation output normal mode Resets the overflow mode to zeroAfter execution completes 14.61 RPT Repeat Next InstructionIf RPT adrs8 Load src to repeat counter Load imm8 to repeat counterRtag *R6+0x0003 Rtag Reset TagStag , Rflag , Sflag Rtag *R6+0x0002SXM 14.63 RXM Reset Extended Sign ModeAssembly Language Instructions 159 STAT.XM160 Address flagadrs only accesses the 17 th bitSflag Set Memory Flag Rflag , Stag , RtagSet fractional mode. Set FM bit of Stat to 14.65 SFM Set Fractional ModeMode for signed fractional arithmetic Assembly Language Instructions 161Shls 14.66 SHL Shift LeftPH , PL Accumulator. Use Shlac for this purposeExample 4.14.67.2 Shlac A1~, A1, --A Shlac Shift Left AccumulatorIts offset. LSB of result is set to zero Shift accumulator A1 by one bit to the left164 Shlacs Shift Left Accumulator String IndividuallyAccumulators in the string Example 4.14.69.3 Shlapl A1, A1, ++A Shlapl Shift Left with AccumulateExample 4.14.69.1 Shlapl A0, *R4++R5 Shlapl A2, *R1++Shift a n ~ string left, addb PL to a n ~ Shlapls Shift Left String With AccumulateShift data memory string left, add PL to a n An~ Assembly Language Instructions 167Shls Shift Left Accumulator String to Product Execution PH, PLExample 4.14.72.3 Shlspl A1, A1, ++A Shlspl Shift Left With Subtract PLExample 4.14.72.1 Shlspl A0, *R4++R5 Shlspl A2, *R1++Shift RAM string left, subtract PL from An Assembly Language Instructions 169Shlspls Shift Left String With Subtract PL NS+3 NR+3Example 4.14.74.3 Shltpl A1, A1, ++A Shltpl Shift Left and Transfer PL to AccumulatorExample 4.14.74.1 Shltpl A0, *R4++R5 Shltpl A2, *R1++Shift the accumulator string A1 by nSV bits to the left Shltpls Shift Left String and Transfer PL to AccumulatorReceives the same data as PH SHLTPL, SHLAPL, SHLAPLS, SHLSPL, ShlsplsExample 4.14.76.2 Shrac A1~, A1, ++A Shrac Shift Accumulator RightRegister Shift right one bit the accumulator A1Shltpls Assembly Language Instructions 173Shracs Shift Accumulator String Right SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, ShltplSTAT.OM Set Overflow Mode SyntaxOutput DSP mode SovmStag *0x401 StagRTAG, RFLAG, Sflag An ~ , An ~ , imm16 , next a 14.80 SUB SubtractDest, src , src1 , next a An ~ , An , adrs , next aSUB R3, R5 Example 4.14.80.2 SUB A0, A0, 2, ++ASUB A1, A1~, A1 SUB A3~, A3, *R4Syntax Description Subb a n, imm8 Subb Subtract ByteSubtract 0x45 from accumulator A2 byte Subtract 0xF2 from register R3 byteNR+2 Assembly Language Instructions 179Subs Subtract Accumulataor String 180 Subs A2, A2, A2~Subs A2, A2~, A2 Subs A3~, A3~, PHRXM 14.83 SXM Set Extended Sign ModeSets extended sign mode status register Stat bit 0 to Assembly Language Instructions 181See Also RET, IRET, CALL, C cc Example Vcall Vectored CallPush PC + 0x7F00 R7 R7 + Flags AffectedTAG bit is set accordingly Src is flagadrs 14.85 XOR Logical XORXOR src For two operands XOR src For three operandsExample 4.14.85.2 XOR A0, A0, 2, ++A XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsExample 4.14.85.1 XOR A1, A1, 0x13FF XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Assembly Language Instructions 185Xorb Logical XOR Byte Xors A2, A2~, A2 Xors Logical XOR StringDest string XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, NotacsZAC A1~, ++A 14.88 ZAC Zero AccumulatorPC PC + Flags Affected ZF = ZacsZAC Reset the content of offset accumulator string A1~ to zeroZacs Zero Accumulator String Zero the specified accumulator stringInstruction Set Encoding Assembly Language Instructions 189Instruction Set Encoding 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 Assembly Language Instructions 195 196 Description True condition Not true condition Assembly Language Instructions 197Instruction Set Summary An, An~ Pma16 , Rmod Assembly Language Instructions 199An~, An~ , next a An~, pma16MR , imm16 , next a Adrs, a n~ , next a~, adrs , next a An ~, imm16 , next aFlagadrs† , TFn Assembly Language Instructions 201Adrs, TOS STR, adrsAdrs An ~, An ~, imm16 , next a ~, a n~, a n , next a ~ , next a~, a n~ , next a ~ , a n~An~, An~, An An~, An~ , next a NR+3 Assembly Language Instructions 203TFn, flagadrs NR+3 TFn, cc , Rx An~, An~, pma16~, a n~, PH ~, a n~~, a n, a n~ , next a ~, a n, a n~Conditional on ZF=0 and SF=1 Not condition ZF≠ Or SF≠ Conditional on RCF=1 Not condition RCF=0Conditional on RZF=0 and RCF=1 Not condition RZF≠ 0 or RCF≠ Conditional on RZF=1 Not condition RZF=0Instruction Set Summay 206Assembly Language InstructionsMC = Pllm value+1 ⋅ 131.07 kHz 208Assembly Language Instructions Summay Language Instructions209 Instruction Set Summay 210Assembly Language Instructions Code Development Tools Introduction Code Development Tools Pin IDC Connector top view looking at the boardMSP50C6xx Development Tools Guidelines MSP50C6xx Development Tools GuidelinesCategories of MSP50Cxx Development Tools SDK50P614 kit of 15 MSP50P614sSPEECH-EVM†PC50C604† Tools DefinitionsMSP50C6xx Development Tools Guidelines Software Tools-Definitions System Requirements MSP50C6xx Code Development ToolsDocumentation Hardware Tools Setup Green Target board power Red MSPSCANPORTI/F power YellowAssembler AssemblerAssembler Directives Examples#ELSE see #IF and #IFDEF An assembly language program#ENDIF #IF expression Do something here#ELSE Do other things here#IFNDEF symbol Example #IFDEF symbolAssembler Compiler CompilerForeword Type Name Mnemonic Range Size in Bytes Example Variable TypesExternal References With Arguments Defines a replacement string for a given stringDirectives Without ArgumentsSee #if directive Include Files#define STRLENGTHi Major Differences between C and C Initialization values are stored in program memory Function Prototypes and DeclarationsInitializations RAM UsageOperator can take the following values predefined constants String FunctionsString Functions An example of the use of xferconst is Constant FunctionsSigned comparison of a and b. a is in A0, b is in A0~ Implementation DetailsComparisons This section is C- specificUgt Assembly VectorUnsigned comparison of a and b. a is in A0, b is in A0~ UltLow Address High Address DivisionFunction Calls Stack frame has the following structureOn RET Programming ExampleCmmfunc bidonint i1,char *i2 is valid, but On Call#include cmmmacr.h Reserved Programming Example, C -- With Assembly RoutinesImplementation Details R7Param Addb R7,2 To C function return in roncoreturn OldR5 Return Addr Param R7,R5 Stack data Param R7,R5 Stack data Before call Parameter Return Addr Param Stack data Efficiency EfficiencyTo ASM function return Efficiency Example 5-1. First Project Real Time Clock ExampleJrtc.rpj Hmodules MAINRAM.IRX Allocated by changingEfficiency CMM1.ASM Allocated as follows Sixth file, cmm1ram.asm, allocates memory for cmm1.asmMAIN.CMM Example 5-2. Second Project C-- With Speech Isr Tim2isr.asm dacisr.asm J tim1isr.asm Celp Celp.irxUtil.obj Dspvar.irx dsputil.asm getbits.asm speak.asm speak.irxDsp Tens.qfmMelp Ampm.qfmRamendcustomer Ramstartcustomer Clock will need to say Assembly routines that will be called are declared externalNew C-- callable functions were declared global Cmmfunc speakHours Example 5-3. Third Project C-- with an LCD Celp Ampm.qfm Days.qfm Ones.qfm Teens.qfm Melp.irx Melp.objLcd Lcd.asm Lcd.irx External lcdsetio external lcdinit Case Efficiency Beware of Stack Corruption Beware of Stack CorruptionReported Bugs With Code Development Tool Reported Bugs With Code Development ToolApplications Application Circuits Application CircuitsApplications6-3 ∝ F 22 pFMSP50P614 only 100 kΩ 3300 pFInitializing the MSP50C6xx Initializing the MSP50C6xxApplications6-5 File init.asmJNZ Itsacpart Itsappart Applications6-7 TI-TALKS Example Code TI-TALKS Example CodeGetting Started Applications6-9 RAM OverlayCreating a New Project RAM OverlayAdding Customer Variables RAM OverlayCommon Problems Page Customer Information Package Information Mechanical InformationDie Bond-Out Coordinates Customer Information Signal and Pad Descriptions for the MSP50C614Signal and Pad Descriptions for the MSP50C605 Signal and Pad Descriptions for the MSP50C601 Signal and Pad Descriptions for the MSP50C604 Pin QFP Mechanical Information 13 NOM Extra pin 3 4 5 6 7 8 9 10 11 12 13 Bottom View 13 12 11 10 9 8 7 6 5 4 3 2Bottom view Bottom View of 120-Pin PGA Package of the MSP50P6140x0006 Device number 0x0614 Customer Information Fields in the ROMCustomer Information Fields in the ROM Software Design Hardware Design Speech SpecificationSpeech Development Cycle Device Production SequenceDevice Production Sequence Code Letter PJM Loopin 100-Pin QFP Ordering InformationNew Product Release Forms Nprf 6xxNew Product Release Forms Nprf Approval of Prototypes and Authorization to Start Production NEW Product Release Form for MSP50C604 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C605 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C601 Option Selection New Product Release Forms Nprf Topic Additional InformationAdditional Information Additional Information