I/O

3.1.5Internal and External Interrupts

INT3, INT4, INT6, and INT7 are external interrupts which may be triggered by events on the PD2, PD3, PD4, and PD5 pins. These interrupts are supported whether the D-port pins are programmed as inputs or outputs. (When programmed as an output, the pin effectively triggers a software interrupt.)

INT5 is an external interrupt triggered by a falling-edge event on any of the F-port inputs. It is triggered if all eight port-F pins are held high, and then one or more of these pins is taken low.

Only the transition from 0xFFh (all high) to (one or more pins) low will trigger the INT5 event. If any F-port pin is continuously held low and another is toggled high-to-low, no interrupt is detected at the toggling pin. After all F-port pins have been brought high again, then it is possible for a new INT5 trigger to occur.

INT0 is an internal interrupt (highest priority) which is triggered by an underflow condition on the DAC Timer (see Section 3.2.2, DAC Control and Data Registers). INT1 and INT2 are high-priority, internal interrupts triggered by the underflow conditions on TIMER1 and TIMER2, respectively. Please refer to Section 2.8, Timer Registers, for a full description of the TIMER controls and their underflow conditions.

When properly enabled, any of these interrupts may be used to wake the de- vice up from a reduced-power state. In a deep-sleep state, they can also be used to wake the device when used in conjunction with the ARM bit. Please refer to Section 2.11, Reduced Power Modes, for information regarding the MSP50C6xx’s reduced power modes.

Peripheral Functions

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Texas Instruments MSP50C6xx manual Internal and External Interrupts