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Texas Instruments MSP50C6xx manual 208Assembly Language Instructions

Models: MSP50C6xx

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4-208Assembly Language Instructions

Interrupt	Vector	Source	Trigger Event	Priority	Comment
INT0	0x7FF0	DAC Timer	timer underflow	highest	used to synch. speech data

INT1	0x7FF1	TIMER1	timer underflow	2nd
INT2	0x7FF2	TIMER2	timer underflow	3rd
INT3	0x7FF3	port PD2	rising edge	4th	port PD2 goes HIGH
INT4	0x7FF4	port PD3	falling edge	5th	port PD3 goes LOW
INT5	0x7FF5	all port F	any falling edge	6th	F port goes from all–HIGH to LOW
INT6†	0x7FF6	port PD4	rising edge	7th	port PD4 goes HIGH
INT7†	0x7FF7	port PD5	falling edge	lowest	port PD5 goes LOW
RESET	0x7FFF	hardware RESET	active low pulse	nonmaskable	Some internal I/O register

†INT6 and INT7 may be associated instead with the Comparator function, if the Comparator Enable bit has been set. Refer to section 3.3 for details

8 kHz Nominal Synthesis Rate (32.768 kHz oscillator reference)

			ClkSpdCtrl				Output	Number of	Number of
DAC	IntGenCtrl	Over-Sampling	PLLM	Master Clock	PDM	CPU Clock	Sampling	Instructs	Instructs
DAC	PDMCD	Over-Sampling	Register	Rate	Rate	Rate	Rate	btwn DAC	btwn 8 kHz
Precision	Bit	Factor	Value	(Hz)	(Hz)	(Hz)	(Hz)	Interrupts	Interrupts

8 bits	1	1x	0x 0F	2.10 M	2.10 M	1.05 M	8.19 k	128	128
		2x	0x 1E	4.06 M	4.06 M	2.03 M	15.87 k	128	256
		4x	0x 3E	8.26 M	8.26 M	4.13 M	32.26 k	128	512
		8x	0x 7C	16.38 M	16.38 M	8.19 M	64.00 k	128	1024

	0	1x	0x 1E	4.06 M	2.03 M	2.03 M	7.94 k	256	256
		2x	0x 3E	8.26 M	4.13 M	4.13 M	16.13 k	256	512
		4x	0x 7C	16.38 M	8.19 M	8.19 M	32.00 k	256	1024

9 bits	1	1x	0x 1E	4.06 M	4.06 M	2.03 M	7.94 k	256	256
		2x	0x 3E	8.26 M	8.26 M	4.13 M	16.13 k	256	512
		4x	0x 7C	16.38 M	16.38 M	8.19 M	32.00 k	256	1024

	0	1x	0x 3E	8.26 M	4.13 M	4.13 M	8.06 k	512	512
		2x	0x 7C	16.38 M	8.19 M	8.19 M	16.00 k	512	1024

10 bits	1	1x	0x 3E	8.26 M	8.26 M	4.13 M	8.06 k	512	512
		2x	0x 7C	16.38 M	16.38 M	8.19 M	16.00 k	512	1024

	0	1x	0x 7C	16.38 M	8.19 M	8.19 M	8.00 k	1024	1024

Instruction Set Summay

Image 294

Texas Instruments MSP50C6xx manual 208Assembly Language Instructions

Contents

MSP50C6xx Mixed-Signal Processor User’s Guide Important Notice Notational Conventions How to Use This ManualAbout This Manual IiiHere is a sample program listing Csr -a /user/ti/simuboard/utilitiesNotational Conventions This book may contain cautions and warnings Information About Cautions and WarningsTrademarks Information About Cautions and WarningsPage Contents Assembly Language Instructions ContentsPeripheral Functions Contentsix Code Development ToolsApplications Customer InformationContentsxi PLL Performance -27 2-10 Instruction Execution and TimingTables Contentsxiii TablesXiv Introduction to the MSP50C6xx Features of the MSP50C6xx Features of the MSP50C6xxIndustrial ApplicationsConsumer Education Aids for the HandicappedDevelopment Device MSP50P614 Development Device MSP50P614Functional Description for the MSP50C614 Functional Description for the MSP50C614Functional Description for the MSP50C614 Crystal Reference Oscillator Connections Resistor Trim Oscillator ConnectionsReset Circuit MSP50C601, MSP50C604, and MSP50C605 MSP50C601, MSP50C604, and MSP50C605Page MSP50C6xx Architecture Architecture Overview MSP50C6xx Core Processor Block Diagram MSP50C6xx ArchitectureComputational Unit Block Diagram Signed and Unsigned Integer Representation Computation UnitMultiplier Computation UnitComputation Unit Overview of the Multiplier Unit Operation Arithmetic Logic UnitAccumulator Block Overview of the Arithmetic Logic Unit AC Register # Points toPoints to Offset Data Memory Address Unit Data Memory Address UnitRAM Configuration Data Memory Address UnitData Memory Addressing Modes Program Counter Unit Bit Logic UnitProgram Counter Unit Memory Organization RAM and ROM Memory MapMemory Organization RAM and ROM C6xx Memory Map not drawn to scale Peripheral Communications PortsReset LOW Summary of MSP50C614’s Peripheral Communications PortsSummary of C614’s Peripheral Communications Ports Interrupt VectorsInterrupt Name ROM address Event Source Interrupt Priority ROM Code Security Write only Block Protection WordAddress 0x7FFE True Protection Marker N TM≡ the binary complement of N TM = the value programmed at TM5 … TM0 trueProtection marker = the value programmed at FM5 … FM0 falseInterrupt Logic Macro Call VectorsInterrupt Logic Bit wide location 00 ← INT number IFRInterrupt Logic Interrupt Initialization Sequence PLL Performance Clock ControlOscillator Options Clock ControlPLL Performance Clock Speed Control Register Clock frequency kHz = Pllm register value + 1 ⋅ 65.536 kHzRTO Oscillator Trim Adjustment ClkSpdCtrl registerRtrim Register Read Only Applies to MSP50C6xx Device Only ClkSpdCtrl Value Copied ShadedTimer Registers Timer RegistersTimer Registers Reduced Power Modes Reduced Power ModesReduced Power Modes Reduced Power Modes Programmable Bits Needed to Control Reduced Power Modes Deeper sleep … relatively less power → Component DeterminedBy Controls Deeper sleep … Event DeterminedGlobal interrupt enable is SET Execution Timing Execution TimingPeripheral Functions MSP50C614 I/OGeneral-Purpose I/O Ports MSP50C604 MSP50C605Control register address 0x04h† 0x14h 0x1Ch 0x24h Possible control values = High-Z InputPeripheral Functions Dedicated Input Port F Dedicated Output Port G Input Port FData register address Branch on D Port Totem-Pole Output Port GInternal and External Interrupts Interrupts Summary of the interrupts is given in TableInterrupt Vector Source Trigger Event Priority Comment DAC Control and Data Registers Digital-to-Analog Converter DACPulse-Density Modulation Rate Digital-to-Analog Converter DACOverflow bits Least-significant data value Ignored bits PDM Clock Divider PDM Clock DividerDigital-to-Analog Converter DAC Example 3-1 -kHz Sampling Rate DACExample 3-2 -kHz Sampling Rate Comparator INT6 INT7 TIMER1 Enable Comparator IntGenCtrl register Interrupt/General Control RegisterInterrupt/General Control Register Address Bit wide location LowInterrupt/General Control Register Hardware Initialization States Hardware Initialization StatesHardware Initialization States Bit Bit Name Initialized Value Description Assembly Language Instructions Instruction Set SummaryIntroduction System RegistersSystem Registers Assembly Language InstructionsTop of Stack, TOS PostdecrementProduct High Register PH Product Low Register PLAccumulators AC0-AC31 Bit Accumulator Pointers AP0-AP3Indirect Register R0-R7 Bits 16String Register STR Status Register StatStatus Register Stat FunctionInstruction Syntax and Addressing Modes 1 MSP50P614/MSP50C614 Instruction SyntaxBit Opcode Addressing Mode EncodingAddressing Modes Next aAddressing Mode Bits and adrs Field Description Rx Bit DescriptionMSP50P614/MSP50C614 Addressing Modes Summary Auto Increment and Auto Decrement ModesFlagadrs Flag addressing mode encoding, flagadrsFlag Repeat Clocks Words Addressing Operation, † SyntaxExample Immediate AddressingSyntax ADD AP0, 0x1AMulr *0x02A1 Direct AddressingMOV *0x012F * 2, *A0 Memory OperandSyntaxOperation Indirect AddressingIndirect Addressing Syntax Rx x = 0 Address Memory Operand ++  --  ++R5*R4++ Relative AddressingMOV A2, *R0 Movb *R7++, A3A0, *R3+R5 Rx x = 0 Address Index Register R5 OperandR6 page register Address Bit positive offset Operand MOV A3, *R6+0x10 Rx x = 0 Address Memory OperandOr TF2, *R6+0x02 Flag AddressingTF1, *0x20 XOR TF1, *R6+0x208 Tag/Flag Bits Possible sources of confusion Consider the following code TF1,*ram1 TF1 bit in Stat is set!?Instruction Classification 10. Symbols and ExplanationSymbol Explanation Instruction ClassificationNext a Accumulator control bits as described in Table 11. Symbols and Explanation11. Instruction Classification Class Sub- DescriptionClass Sub Description 12. Classes and Opcode Definition Class 1 Instructions Memory and Accumulator ReferenceC1a ~A~ 13. Class 1 Instruction Encoding14. Class 1a Instruction Description C1b15. Class 1b Instruction Description C1b Mnemonic DescriptionClass 2 Instructions Accumulator and Constant Reference 16. Class 2 Instruction Encoding 17. Class 2a Instruction DescriptionC2a Mnemonic Description C2b Mnemonic Description 18. Class 2b Instruction DescriptionClass 3 Instruction Accumulator Reference ADD An ~, An ~, imm16 , next aMnemonic Description 19. Class 3 Instruction Encoding20. Class 3 Instruction Description Subs An~, An~, An Modified ADD An~, An~, An , next aALU status is modified. String bit causes subtract with Zero or be set equal to the sign bit Xsgm dependentSUB a n~, a n~, PH , next a Carry status CFIs modified PH msbs extended by XM mode bit. Transfer the lowerMOV SV, An~ , next a From the offset accumulator A~=1 or accumulatorClass 4 Instructions Address Register and Memory Reference 21. Class 4a Instruction Encoding24. Class 4c Instruction Description 22. Class 4a Instruction Description23. Class 4b Instruction Description 25. Class 4d Instruction Description27. Class 5 Instruction Description Class 5 Instructions Memory Reference26. Class 5 Instruction Encoding Adrs. Transfer status is modifiedStag adrs Dressing mode adrs. Transfer status is modifiedMOV adrs, TOS Tag bit29. Class 6a Instruction Description Class 6 Instructions Port and Memory Reference28. Class 6a Instruction Encoding C6a Mnemonic Description30. Class 6b Instruction Description Class 7 Instructions Program ControlC6b Mnemonic Description Jcc 31. Class 7 Instruction Encoding and DescriptionVector8 CccClass 8 Instructions Logic and Bit 32. Class 8a Instruction EncodingClass 9 Instructions Miscellaneous 33. Class 8a Instruction Description34. Class 8b Instruction Description C8a Mnemonic Description37. Class 9b Instruction Description 35. Class 9a Instruction Encoding36. Class 9a Instruction Description C9a Mnemonic Description39. Class 9d Instruction Description Bit, Byte, Word and String Addressing38. Class 9c Instruction Description C9c Mnemonic DescriptionWord Global Flags Relative0000h 0001h 0002h 0040h 0041h Nnnn 17th Bit 0000h MS Byte LS ByteMovb A0, *0x0003 Mode Address Used Data Order Rx Post modify †40. Data Memory Address and Data Relationship MOV A0, *0x0004Which uses the absolute word memory address Rflag MSP50P614/MSP50C614 Computational Modes MSP50P614/MSP50C614 Computational ModesComputational Setting Resetting Function Mode Instruction 41. MSP50P614/MSP50C614 Computational ModesSXM Example 4.6.1 Sovm Example 4.6.2 SovmExample 4.6.1 SXM Hardware Loop Instructions Hardware Loop Instructions42. Hardware Loops in MSP50P614/MSP50C614 Syntax Operation LimitationsCompletion of the BEGLOOP/ENDLOOP block Data memory *address = data String Instructions43. Initial Processor State for String Instructions Program memory *address = dataMulapl A0, A0~ Lookup Instructions Lookup Instructions44. Lookup Instructions Instructions Description Data TransferMOV An, adrs SUB An MOV An, *An Input/Output Instructions Input/Output InstructionsSpecial Filter Instructions Xk-2 Xk+2 Xk-1 xk+1 32 orSpecial Filter Instructions Special Filter Instructions STR,0 0x0106 0x0100 0x01020x0104 Go back N words to wrap aroundAfter FIR/COR execution Important Note About Setting the Stat Register Firkcoeffs FIR/COR only = 0..N Coeffarray address FIRK/CORK only Program memory FIRK/CORKCoeffarray Samplebuf address CoeffarraySamplebuf Coeffarray is stored Conditionals ConditionalsOffset16 ≤ Symbol MeaningOperands Port4 ≤ Port6 ≤Dma n AdrsnClk FlgOffset n Pma nPort n 46. Addressing Mode Bits and adrs Field Description 45. Auto Increment and Decrement47. Flag Addressing Syntax and BIts Individual Instruction Descriptions Individual Instruction Descriptions14.1 ADD Add word ExecutionDescription See AlsoAddb PC PC + Flags AffectedOpcode Adds Add String Clock , clk Words , wAdds A1, A1~, A1 14.4 Bitwise ANDS, ANDB, OR, ORB, ORS, XOR, XORB, Xors A3, *R4TF2, *0x0020 OF, SF, ZF, CF are set accordingly Andb Bitwise and ByteSrc byte PC PC + Clock , clk Word , wAnds Bitwise and String Ands A0, A0~, A0Ands A0, A0~, *R2 Flags Affected None Opcode Begloop Begin LoopSave next instruction address PC + Order to loop N timesCall Unconditional Subroutine Call RET 14.9 Ccc TOSNOP 48. Names for cc True condition Not true conditionSyntax Alternate Syntax Description CTF1 CALL, VCALL, RET, Iret0x2010 CrnbePC = PC + w 14.10 CMP Compare Two WordsStat flags set by src src1 operation CMPB, CMPS, Jcc, CccCMP R2, 0xfe20 CMP R0, R5Cmpb Compare Two Bytes Cmpb R3Cmps A1~ Cmps Compare Two StringsPC PC + w Flags Affected Cmps A2, A2~An, *Rx 3nR+2 With RPT instruction. See .11 for more detail on the setup14.13 COR Correlation Filter Function Rxeven = Rxeven + R53n R+2 Cork Correlation Filter FunctionSample data. During Cork execution, interrupt is queued Xeven = R xeven + R5Argument, it assumes n =1 Endloop End LoopDecrement R4 by n 1 or PC first address after Begloop else BEGLOOP, InteCopy accumulator sign flag SF to all 16 bits of a n ~ Extsgn Sign Extend Word~ , next a Dest , modExtsgns Sign Extend String An~100 An, *Rx 2nR+2 Assembly Language Instructions 10114.18 FIR FIR Filter Function Coefficients in RAM Rxeven++102 Assembly Language Instructions 103 FirkIdle Halt Processor 10414.21 Input From Port Into Word INS, OUT, OutsA2~, 0x3d 14.22 INS Input From Port Into String IN, OUT, OutsSTAT.IM Intd Interrupt DisableAssembly Language Instructions 107 IM is Stat bit PC PC + Flags Affected None OpcodeINTD, Iret Interrupt EnableInte Clock, clk Word, w With RPT, clk ClassAssembly Language Instructions 109 Iret Return From InterruptConditional Jumps RCF and RZF affected by post-modification of RAssembly Language Instructions 111 Cc namesIf test condition is false, a NOP is executed JE 0x2010, R3++R5 See Also JMP, CALL, C cc ExampleJNZ Jtag 0x2010, R2++See Also Cc, CALL, C cc Example 14.27 JMP Unconditional JumpPost-modify R x if specified Instruction Operation14.28 MOV Move Data Word From Source to Destination TF n, cc , R XSF, XZF are set accordinglyClock , clk Word , w With RPT , clk Class STR, imm8Assembly Language Instructions 117 MOV adrs, DPWith some operand types Example 4.14.28.11 MOV A1~, *A1 MOVU, MOVT, MOVB, MOVBS, MovsExample 4.14.28.10 MOV MR, A3, --A Example 4.14.28.12 MOV *0x0200 * 2, R0Transfer R5 to R0 Example Example 4.14.28.13 MOV R1, 0x0200Example 4.14.28.15 MOV *0x0200 * 2, R0 Example 4.14.28.18 MOV *R6 + 8 * 2, DPMovaph Move With Adding PH Execution An + PHMOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs Background. See .8 for more details Movaphs Move With Adding PHExecution + PH MOVAPH, MOVTPH, MOVTPHS, MOVSPH, MovsphsMovb A0, *R2 Movb Move Byte From Source to DestinationCopy value of unsigned src byte to dest byte Copy data memory byte pointed by R2 to accumulator A0Movb *R2, A0 Movb A0, 0xf2Movb R2 Movbs A2, *0x0200 Movbs Move Byte String from Source to DestinationTAG bit is set to bit 17th value Movbs *0x0200, A2Adrs , An ~ Movs Move String from Source to DestinationAn ~ , adrs Adrs , *AnMovs A1, A1~ MOVU, MOV, MOVT, MOVB, MovbsMovs A2~ Movs A1~, A1Movsph MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs128 Movsphs Move String With Subtract From PH An second word PH MR contents of adrsAssembly Language Instructions 129 DetailsAvailable MovtPC PC + w Flags Affected None Opcode MOVU, MOV, MOVT, MOVB, MOVBS, MovsMOV, MOVB, MOVT, MOVBS, Movs Movu Move Data UnsignedTAG bit is set accordingly UM is set to Copy the value pointed by R3 to MRMR/SV An S APn Xxxxxx Xxxx00 Flag Bit132 Accumulator pointer if specified 14.38 MUL Multiply RoundedMR * src PC PC + w Flags Affected MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, MulaplMULS, MUL, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls Mulr Multiply Rounded With No Data TransferMR * src PC PC + Flags Affected MulaplMuls Multiply String With No Data Transfer Length nS+2, where nS is the value in STR registerAssembly Language Instructions 135 PH,PL MR * src stringBackground. See .8 for more detail Mulapl Multiply and Accumulate ResultPH ,PL MR * src MULAPLS, MULSPL, MULSPLS, MULTPL, MultplsMulapls Multiply String and Accumulate Result MR * srcMULAPL, MULSPL, MULSPLS, MULTPL, Multpls MULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls Mulspl Multiply and Subtract PL From AccumulatorOccuring in the background. See .8 for more details Syntax Description Mulspl adrsMULSPL, MULTPL, MULTPLS, MULAPL, Mulapls Mulspls Multiply String and Subtract PL From AccumulatorFrom dest string Syntax Description Mulspls adrsValue of src. The 16 MSBs Multpl Multiply and Transfer PL to Accumulator~ , a n ~ , next a Multiply MR by data memory word, move PL to a nMULTPL, MULAPL, MULAPLS, MULSPL, Mulspls MultplsExecution PH, PL MR * src PC PC + Flags Affected Example 4.14.46.2 Multpls A2, A2~NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs Negac Two’s Complement Negation of AccumulatorAccumulator Example 4.14.47.1 Negac A3~, A3, --ADest accumulator string Assembly Language Instructions 143Negacs Two’s Complement Negation of Accumulator String NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs14.49 NOP No Operation Execution PC PC +RPT NEGAC, Negacs Notac One’s Complement Negation of AccumulatorNOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors Example 4.14.50.1 Notac A3~, A3, --ANegacs Notacs One’s Complement Negation of Accumulator StringAccumulator string A3~14.52 or Bitwise Logical or TFn bits in Stat register are set accordinglyAccumulator pointers are allowed with some operand types Or TF1, *R6+0x22 ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOr A0, *R0++R5 148Accumulator is affected 14.53 ORB Bitwise or ByteOr src OR, ORS, AND, ANDS, XOR, XORS, NOTAC, NotacsOR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs 14.54 ORS Bitwise or StringPC + w Flags Affected ORS A0, A0~, A014.55 OUT Address is multipled by 4 to get the actual port addressOUTS, IN, INS OUT, IN, INS Outs Output String to PortPort6 specified in the instruction Port6 , An ~R7 R7 Flags Affected 14.57 RET Return From Subroutine CALL, CccPC TOS CALL, i.e., RET followed by a RET should not be allowedRflag Reset Memory Flag Sflag , Stag , RtagExample 4.14.58.2 Rflag *R6 + 14.59 RFM Reset Fractional Mode SyntaxResets the fractional mode. Clears FM bit of Stat STAT.FMResets the overflow mode to zero Rovm Reset Overflow ModeSaturation output normal mode Stat .OMLoad imm8 to repeat counter 14.61 RPT Repeat Next InstructionIf RPT adrs8 Load src to repeat counter After execution completesRtag *R6+0x0002 Rtag Reset TagStag , Rflag , Sflag Rtag *R6+0x0003STAT.XM 14.63 RXM Reset Extended Sign ModeAssembly Language Instructions 159 SXMRflag , Stag , Rtag Address flagadrs only accesses the 17 th bitSflag Set Memory Flag 160Assembly Language Instructions 161 14.65 SFM Set Fractional ModeMode for signed fractional arithmetic Set fractional mode. Set FM bit of Stat toAccumulator. Use Shlac for this purpose 14.66 SHL Shift LeftPH , PL ShlsShift accumulator A1 by one bit to the left Shlac Shift Left AccumulatorIts offset. LSB of result is set to zero Example 4.14.67.2 Shlac A1~, A1, --AShlacs Shift Left Accumulator String Individually Accumulators in the string164 Shlapl A2, *R1++ Shlapl Shift Left with AccumulateExample 4.14.69.1 Shlapl A0, *R4++R5 Example 4.14.69.3 Shlapl A1, A1, ++AShlapls Shift Left String With Accumulate Shift data memory string left, add PL to a nShift a n ~ string left, addb PL to a n ~ Execution PH, PL Assembly Language Instructions 167Shls Shift Left Accumulator String to Product An~Shlspl A2, *R1++ Shlspl Shift Left With Subtract PLExample 4.14.72.1 Shlspl A0, *R4++R5 Example 4.14.72.3 Shlspl A1, A1, ++ANS+3 NR+3 Assembly Language Instructions 169Shlspls Shift Left String With Subtract PL Shift RAM string left, subtract PL from AnShltpl A2, *R1++ Shltpl Shift Left and Transfer PL to AccumulatorExample 4.14.74.1 Shltpl A0, *R4++R5 Example 4.14.74.3 Shltpl A1, A1, ++ASHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls Shltpls Shift Left String and Transfer PL to AccumulatorReceives the same data as PH Shift the accumulator string A1 by nSV bits to the leftShift right one bit the accumulator A1 Shrac Shift Accumulator RightRegister Example 4.14.76.2 Shrac A1~, A1, ++ASHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl Assembly Language Instructions 173Shracs Shift Accumulator String Right ShltplsSovm Set Overflow Mode SyntaxOutput DSP mode STAT.OMStag RTAG, RFLAG, SflagStag *0x401 An ~ , An , adrs , next a 14.80 SUB SubtractDest, src , src1 , next a An ~ , An ~ , imm16 , next aSUB A3~, A3, *R4 Example 4.14.80.2 SUB A0, A0, 2, ++ASUB A1, A1~, A1 SUB R3, R5Subtract 0xF2 from register R3 byte Subb Subtract ByteSubtract 0x45 from accumulator A2 byte Syntax Description Subb a n, imm8Assembly Language Instructions 179 Subs Subtract Accumulataor StringNR+2 Subs A3~, A3~, PH Subs A2, A2, A2~Subs A2, A2~, A2 180Assembly Language Instructions 181 14.83 SXM Set Extended Sign ModeSets extended sign mode status register Stat bit 0 to RXMR7 R7 + Flags Affected Vcall Vectored CallPush PC + 0x7F00 See Also RET, IRET, CALL, C cc ExampleXOR src For three operands 14.85 XOR Logical XORXOR src For two operands TAG bit is set accordingly Src is flagadrsXORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Example 4.14.85.1 XOR A1, A1, 0x13FFExample 4.14.85.2 XOR A0, A0, 2, ++A Assembly Language Instructions 185 Xorb Logical XOR ByteXOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs Xors Logical XOR StringDest string Xors A2, A2~, A2Zacs 14.88 ZAC Zero AccumulatorPC PC + Flags Affected ZF = ZAC A1~, ++AZero the specified accumulator string Reset the content of offset accumulator string A1~ to zeroZacs Zero Accumulator String ZACAssembly Language Instructions 189 Instruction Set EncodingInstruction Set Encoding 190 Assembly Language Instructions 191 192 Assembly Language Instructions 193 194 Assembly Language Instructions 195 196 Assembly Language Instructions 197 Description True condition Not true conditionInstruction Set Summary An~, pma16 Pma16 , Rmod Assembly Language Instructions 199An~, An~ , next a An, An~An ~, imm16 , next a Adrs, a n~ , next a~, adrs , next a MR , imm16 , next aSTR, adrs Assembly Language Instructions 201Adrs, TOS Flagadrs† , TFn~ , a n~ ~ , next a~, a n~ , next a Adrs An ~, An ~, imm16 , next a ~, a n~, a n , next aAn~, An~, pma16 An~, An~ , next a NR+3 Assembly Language Instructions 203TFn, flagadrs NR+3 TFn, cc , Rx An~, An~, An~, a n, a n~ ~, a n~~, a n, a n~ , next a ~, a n~, PHConditional on RZF=1 Not condition RZF=0 Conditional on RCF=1 Not condition RCF=0Conditional on RZF=0 and RCF=1 Not condition RZF≠ 0 or RCF≠ Conditional on ZF=0 and SF=1 Not condition ZF≠ Or SF≠206Assembly Language Instructions Instruction Set SummayMC = Pllm value+1 ⋅ 131.07 kHz 208Assembly Language Instructions Language Instructions 209Summay Instruction Set Summay 210Assembly Language Instructions Code Development Tools Introduction Pin IDC Connector top view looking at the board Code Development ToolsSDK50P614 kit of 15 MSP50P614s MSP50C6xx Development Tools GuidelinesCategories of MSP50Cxx Development Tools MSP50C6xx Development Tools GuidelinesTools Definitions SPEECH-EVM†PC50C604†MSP50C6xx Development Tools Guidelines Software Tools-Definitions MSP50C6xx Code Development Tools DocumentationSystem Requirements Hardware Tools Setup Red MSPSCANPORTI/F power Yellow Green Target board powerExamples AssemblerAssembler Directives AssemblerAn assembly language program #ELSE see #IF and #IFDEFDo other things here #IF expression Do something here#ELSE #ENDIFExample #IFDEF symbol #IFNDEF symbolAssembler Compiler ForewordCompiler Variable Types External ReferencesType Name Mnemonic Range Size in Bytes Example Without Arguments Defines a replacement string for a given stringDirectives With ArgumentsInclude Files See #if directive#define STRLENGTHi Major Differences between C and C RAM Usage Function Prototypes and DeclarationsInitializations Initialization values are stored in program memoryString Functions String FunctionsOperator can take the following values predefined constants Constant Functions An example of the use of xferconst isThis section is C- specific Implementation DetailsComparisons Signed comparison of a and b. a is in A0, b is in A0~Ult Assembly VectorUnsigned comparison of a and b. a is in A0, b is in A0~ UgtStack frame has the following structure DivisionFunction Calls Low Address High AddressOn Call Programming ExampleCmmfunc bidonint i1,char *i2 is valid, but On RET#include cmmmacr.h Programming Example, C -- With Assembly Routines ReservedImplementation Details R7Param Addb R7,2 To C function return in roncoreturn OldR5 Return Addr Param R7,R5 Stack data Param R7,R5 Stack data Before call Parameter Return Addr Param Stack data Efficiency To ASM function returnEfficiency Efficiency Real Time Clock Example Example 5-1. First ProjectJrtc.rpj Hmodules Allocated by changing MAINRAM.IRXEfficiency CMM1.ASM Sixth file, cmm1ram.asm, allocates memory for cmm1.asm Allocated as followsMAIN.CMM Example 5-2. Second Project C-- With Speech Dspvar.irx dsputil.asm getbits.asm speak.asm speak.irx Celp Celp.irxUtil.obj Isr Tim2isr.asm dacisr.asm J tim1isr.asmAmpm.qfm Tens.qfmMelp DspRamendcustomer Ramstartcustomer Assembly routines that will be called are declared external New C-- callable functions were declared globalClock will need to say Cmmfunc speakHours Example 5-3. Third Project C-- with an LCD Melp.irx Melp.obj Lcd Lcd.asm Lcd.irxCelp Ampm.qfm Days.qfm Ones.qfm Teens.qfm External lcdsetio external lcdinit Case Efficiency Beware of Stack Corruption Beware of Stack CorruptionReported Bugs With Code Development Tool Reported Bugs With Code Development ToolApplications Application Circuits Application Circuits3300 pF ∝ F 22 pFMSP50P614 only 100 kΩ Applications6-3Initializing the MSP50C6xx Initializing the MSP50C6xxFile init.asm Applications6-5JNZ Itsacpart Itsappart Applications6-7 TI-TALKS Example Code Getting StartedTI-TALKS Example Code RAM Overlay RAM OverlayCreating a New Project Applications6-9RAM Overlay Adding Customer VariablesCommon Problems Page Customer Information Mechanical Information Die Bond-Out CoordinatesPackage Information Signal and Pad Descriptions for the MSP50C614 Customer InformationSignal and Pad Descriptions for the MSP50C605 Signal and Pad Descriptions for the MSP50C601 Signal and Pad Descriptions for the MSP50C604 Pin QFP Mechanical Information 13 NOM 13 12 11 10 9 8 7 6 5 4 3 2 Extra pin 3 4 5 6 7 8 9 10 11 12 13 Bottom ViewBottom View of 120-Pin PGA Package of the MSP50P614 Bottom viewCustomer Information Fields in the ROM Customer Information Fields in the ROM0x0006 Device number 0x0614 Device Production Sequence Speech SpecificationSpeech Development Cycle Software Design Hardware DesignDevice Production Sequence 6xx Ordering InformationNew Product Release Forms Nprf Code Letter PJM Loopin 100-Pin QFPNew Product Release Forms Nprf Approval of Prototypes and Authorization to Start Production NEW Product Release Form for MSP50C604 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C605 Option Selection New Product Release Forms Nprf NEW Product Release Form for MSP50C601 Option Selection New Product Release Forms Nprf Additional Information TopicAdditional Information Additional Information