MSP50C6xx Mixed-Signal Processor User’s Guide
 Important Notice
 Iii
How to Use This Manual
About This Manual
Notational Conventions
 Csr -a /user/ti/simuboard/utilities
Here is a sample program listing
Notational Conventions
 Information About Cautions and Warnings
Information About Cautions and Warnings
Trademarks
This book may contain cautions and warnings
Page
 Contents
 Contents
Assembly Language Instructions
Peripheral Functions
 Code Development Tools
Contentsix
 Customer Information
Applications
 PLL Performance -27 2-10 Instruction Execution and Timing
Contentsxi
 Tables
 Tables
Contentsxiii
 Xiv
 Introduction to the MSP50C6xx
 Features of the MSP50C6xx
Features of the MSP50C6xx
 Aids for the Handicapped
Applications
Consumer Education
Industrial
 Development Device MSP50P614
Development Device MSP50P614
 Functional Description for the MSP50C614
Functional Description for the MSP50C614
 Functional Description for the MSP50C614
 Resistor Trim Oscillator Connections
Crystal Reference Oscillator Connections
 Reset Circuit
 MSP50C601, MSP50C604, and MSP50C605
MSP50C601, MSP50C604, and MSP50C605
Page
 MSP50C6xx Architecture
 Architecture Overview
 MSP50C6xx Architecture
MSP50C6xx Core Processor Block Diagram
 Computational Unit Block Diagram
 Computation Unit
Computation Unit
Multiplier
Signed and Unsigned Integer Representation
 Computation Unit
 Arithmetic Logic Unit
Overview of the Multiplier Unit Operation
 Accumulator Block
 Overview of the Arithmetic Logic Unit
 Points to
AC Register #
Points to Offset
 Data Memory Address Unit
Data Memory Address Unit
 Data Memory Address Unit
RAM Configuration
 Data Memory Addressing Modes
 Bit Logic Unit
Program Counter Unit
Program Counter Unit
 Memory Map
Memory Organization RAM and ROM
Memory Organization RAM and ROM
 Peripheral Communications Ports
C6xx Memory Map not drawn to scale
 Summary of MSP50C614’s Peripheral Communications Ports
Reset LOW
 Interrupt Vectors
Summary of C614’s Peripheral Communications Ports
Interrupt Name ROM address Event Source Interrupt Priority
 ROM Code Security
 True Protection Marker N TM
Block Protection Word
Address 0x7FFE
Write only
 = the value programmed at FM5 … FM0 false
= the value programmed at TM5 … TM0 true
Protection marker
≡ the binary complement of N TM
 Macro Call Vectors
Interrupt Logic
Interrupt Logic
 IFR
Bit wide location 00 ← INT number
 Interrupt Logic
 Interrupt Initialization Sequence
 Clock Control
Clock Control
Oscillator Options
PLL Performance
 PLL Performance
 Clock frequency kHz = Pllm register value + 1 ⋅ 65.536 kHz
Clock Speed Control Register
 ClkSpdCtrl register
RTO Oscillator Trim Adjustment
 ClkSpdCtrl Value Copied Shaded
Rtrim Register Read Only Applies to MSP50C6xx Device Only
 Timer Registers
Timer Registers
 Timer Registers
 Reduced Power Modes
Reduced Power Modes
 Reduced Power Modes
 Reduced Power Modes
 Programmable Bits Needed to Control Reduced Power Modes
 Component Determined
Deeper sleep … relatively less power →
By Controls
 Event Determined
Deeper sleep …
 Global interrupt enable is SET
 Execution Timing
Execution Timing
 Peripheral Functions
 MSP50C604 MSP50C605
I/O
General-Purpose I/O Ports
MSP50C614
 0x14h 0x1Ch 0x24h Possible control values = High-Z Input
Control register address 0x04h†
Peripheral Functions
 Dedicated Input Port F
 Input Port F
Dedicated Output Port G
Data register address
 Totem-Pole Output Port G
Branch on D Port
 Internal and External Interrupts
 Summary of the interrupts is given in Table
Interrupts
Interrupt Vector Source Trigger Event Priority Comment
 Digital-to-Analog Converter DAC
Digital-to-Analog Converter DAC
Pulse-Density Modulation Rate
DAC Control and Data Registers
 Overflow bits Least-significant data value Ignored bits
 PDM Clock Divider
PDM Clock Divider
 Digital-to-Analog Converter DAC
 DAC
Example 3-1 -kHz Sampling Rate
 Example 3-2 -kHz Sampling Rate
 Comparator
 INT6 INT7 TIMER1 Enable
 Comparator
 Address Bit wide location Low
Interrupt/General Control Register
Interrupt/General Control Register
IntGenCtrl register
 Interrupt/General Control Register
 Hardware Initialization States
Hardware Initialization States
 Hardware Initialization States
 Bit Bit Name Initialized Value Description
 Instruction Set Summary
Assembly Language Instructions
 System Registers
Introduction
 Postdecrement
Assembly Language Instructions
Top of Stack, TOS
System Registers
 Product Low Register PL
Product High Register PH
Accumulators AC0-AC31
 Bits 16
Accumulator Pointers AP0-AP3
Indirect Register R0-R7
Bit
 Status Register Stat
String Register STR
 Function
Status Register Stat
 1 MSP50P614/MSP50C614 Instruction Syntax
Instruction Syntax and Addressing Modes
 Next a
Addressing Mode Encoding
Addressing Modes
Bit Opcode
 Rx Bit Description
Addressing Mode Bits and adrs Field Description
 Auto Increment and Auto Decrement Modes
MSP50P614/MSP50C614 Addressing Modes Summary
 Clocks Words Addressing Operation, † Syntax
Flag addressing mode encoding, flagadrs
Flag Repeat
Flagadrs
 ADD AP0, 0x1A
Immediate Addressing
Syntax
Example
 Memory Operand
Direct Addressing
MOV *0x012F * 2, *A0
Mulr *0x02A1
 Rx x = 0 Address Memory Operand ++  --  ++R5
Indirect Addressing
Indirect Addressing Syntax
SyntaxOperation
 Movb *R7++, A3
Relative Addressing
MOV A2, *R0
*R4++
 Rx x = 0 Address Index Register R5 Operand
A0, *R3+R5
R6 page register Address Bit positive offset Operand
 Rx x = 0 Address Memory Operand
MOV A3, *R6+0x10
 XOR TF1, *R6+0x20
Flag Addressing
TF1, *0x20
Or TF2, *R6+0x02
 8 Tag/Flag Bits
 TF1,*ram1 TF1 bit in Stat is set!?
Possible sources of confusion Consider the following code
 Instruction Classification
10. Symbols and Explanation
Symbol Explanation
Instruction Classification
 Class Sub- Description
11. Symbols and Explanation
11. Instruction Classification
Next a Accumulator control bits as described in Table
 Class Sub Description
 Class 1 Instructions Memory and Accumulator Reference
12. Classes and Opcode Definition
 C1b
13. Class 1 Instruction Encoding
14. Class 1a Instruction Description
C1a ~A~
 C1b Mnemonic Description
15. Class 1b Instruction Description
 Class 2 Instructions Accumulator and Constant Reference
 17. Class 2a Instruction Description
16. Class 2 Instruction Encoding
C2a Mnemonic Description
 ADD An ~, An ~, imm16 , next a
18. Class 2b Instruction Description
Class 3 Instruction Accumulator Reference
C2b Mnemonic Description
 Subs An~, An~, An Modified ADD An~, An~, An , next a
19. Class 3 Instruction Encoding
20. Class 3 Instruction Description
Mnemonic Description
 Carry status CF
Zero or be set equal to the sign bit Xsgm dependent
SUB a n~, a n~, PH , next a
ALU status is modified. String bit causes subtract with
 From the offset accumulator A~=1 or accumulator
PH msbs extended by XM mode bit. Transfer the lower
MOV SV, An~ , next a
Is modified
 21. Class 4a Instruction Encoding
Class 4 Instructions Address Register and Memory Reference
 25. Class 4d Instruction Description
22. Class 4a Instruction Description
23. Class 4b Instruction Description
24. Class 4c Instruction Description
 Adrs. Transfer status is modified
Class 5 Instructions Memory Reference
26. Class 5 Instruction Encoding
27. Class 5 Instruction Description
 Tag bit
Dressing mode adrs. Transfer status is modified
MOV adrs, TOS
Stag adrs
 C6a Mnemonic Description
Class 6 Instructions Port and Memory Reference
28. Class 6a Instruction Encoding
29. Class 6a Instruction Description
 Class 7 Instructions Program Control
30. Class 6b Instruction Description
C6b Mnemonic Description
 Ccc
31. Class 7 Instruction Encoding and Description
Vector8
Jcc
 32. Class 8a Instruction Encoding
Class 8 Instructions Logic and Bit
 C8a Mnemonic Description
33. Class 8a Instruction Description
34. Class 8b Instruction Description
Class 9 Instructions Miscellaneous
 C9a Mnemonic Description
35. Class 9a Instruction Encoding
36. Class 9a Instruction Description
37. Class 9b Instruction Description
 C9c Mnemonic Description
Bit, Byte, Word and String Addressing
38. Class 9c Instruction Description
39. Class 9d Instruction Description
 0000h MS Byte LS Byte
Global Flags Relative
0000h 0001h 0002h 0040h 0041h Nnnn 17th Bit
Word
 MOV A0, *0x0004
Mode Address Used Data Order Rx Post modify †
40. Data Memory Address and Data Relationship
Movb A0, *0x0003
 Which uses the absolute word memory address
 Rflag
 MSP50P614/MSP50C614 Computational Modes
MSP50P614/MSP50C614 Computational Modes
 41. MSP50P614/MSP50C614 Computational Modes
Computational Setting Resetting Function Mode Instruction
 SXM
 Example 4.6.2 Sovm
Example 4.6.1 Sovm
Example 4.6.1 SXM
 Hardware Loop Instructions
Hardware Loop Instructions
 Syntax Operation Limitations
42. Hardware Loops in MSP50P614/MSP50C614
Completion of the BEGLOOP/ENDLOOP block
 Program memory *address = data
String Instructions
43. Initial Processor State for String Instructions
Data memory *address = data
 Mulapl A0, A0~
 Instructions Description Data Transfer
Lookup Instructions
44. Lookup Instructions
Lookup Instructions
 MOV An, adrs SUB An MOV An, *An
 Xk-2 Xk+2 Xk-1 xk+1 32 or
Input/Output Instructions
Special Filter Instructions
Input/Output Instructions
 Special Filter Instructions
 Special Filter Instructions
 STR,0
 Go back N words to wrap around
0x0100 0x0102
0x0104
0x0106
 After FIR/COR execution
 Important Note About Setting the Stat Register
 Firkcoeffs
 Coeffarray
Coeffarray address FIRK/CORK only Program memory FIRK/CORK
Coeffarray Samplebuf address
FIR/COR only = 0..N
 Samplebuf Coeffarray is stored
 Conditionals
Conditionals
 Port4 ≤ Port6 ≤
Symbol Meaning
Operands
Offset16 ≤
 Flg
Adrsn
Clk
Dma n
 Pma n
Offset n
Port n
 45. Auto Increment and Decrement
46. Addressing Mode Bits and adrs Field Description
47. Flag Addressing Syntax and BIts
 Individual Instruction Descriptions
Individual Instruction Descriptions
 Execution
14.1 ADD Add word
 See Also
Description
 PC PC + Flags Affected
Addb
Opcode
 Clock , clk Words , w
Adds Add String
 Adds A1, A1~, A1
 14.4 Bitwise
 A3, *R4
ANDS, ANDB, OR, ORB, ORS, XOR, XORB, Xors
TF2, *0x0020
 Clock , clk Word , w
Andb Bitwise and Byte
Src byte PC PC +
OF, SF, ZF, CF are set accordingly
 Ands A0, A0~, A0
Ands Bitwise and String
Ands A0, A0~, *R2
 Order to loop N times
Begloop Begin Loop
Save next instruction address PC +
Flags Affected None Opcode
 Call Unconditional Subroutine Call
 RET
 TOS
14.9 Ccc
NOP
 True condition Not true condition
48. Names for cc
 Syntax Alternate Syntax Description
 Crnbe
CALL, VCALL, RET, Iret
0x2010
CTF1
 CMPB, CMPS, Jcc, Ccc
14.10 CMP Compare Two Words
Stat flags set by src src1 operation
PC = PC + w
 CMP R0, R5
CMP R2, 0xfe20
 Cmpb R3
Cmpb Compare Two Bytes
 Cmps A2, A2~
Cmps Compare Two Strings
PC PC + w Flags Affected
Cmps A1~
 Rxeven = Rxeven + R5
With RPT instruction. See .11 for more detail on the setup
14.13 COR Correlation Filter Function
An, *Rx 3nR+2
 Xeven = R xeven + R5
Cork Correlation Filter Function
Sample data. During Cork execution, interrupt is queued
3n R+2
 BEGLOOP, Inte
Endloop End Loop
Decrement R4 by n 1 or PC first address after Begloop else
Argument, it assumes n =1
 Dest , mod
Extsgn Sign Extend Word
~ , next a
Copy accumulator sign flag SF to all 16 bits of a n ~
 An~
Extsgns Sign Extend String
 100
 Rxeven++
Assembly Language Instructions 101
14.18 FIR FIR Filter Function Coefficients in RAM
An, *Rx 2nR+2
 102
 Firk
Assembly Language Instructions 103
 104
Idle Halt Processor
 INS, OUT, Outs
14.21 Input From Port Into Word
A2~, 0x3d
 IN, OUT, Outs
14.22 INS Input From Port Into String
 IM is Stat bit PC PC + Flags Affected None Opcode
Intd Interrupt Disable
Assembly Language Instructions 107
STAT.IM
 Clock, clk Word, w With RPT, clk Class
Interrupt Enable
Inte
INTD, Iret
 Iret Return From Interrupt
Assembly Language Instructions 109
 RCF and RZF affected by post-modification of R
Conditional Jumps
 Cc names
Assembly Language Instructions 111
 If test condition is false, a NOP is executed
 Jtag 0x2010, R2++
See Also JMP, CALL, C cc Example
JNZ
JE 0x2010, R3++R5
 Instruction Operation
14.27 JMP Unconditional Jump
Post-modify R x if specified
See Also Cc, CALL, C cc Example
 14.28 MOV Move Data Word From Source to Destination
 STR, imm8
XSF, XZF are set accordingly
Clock , clk Word , w With RPT , clk Class
TF n, cc , R
 MOV adrs, DP
Assembly Language Instructions 117
 With some operand types
 Example 4.14.28.12 MOV *0x0200 * 2, R0
MOVU, MOVT, MOVB, MOVBS, Movs
Example 4.14.28.10 MOV MR, A3, --A
Example 4.14.28.11 MOV A1~, *A1
 Example 4.14.28.18 MOV *R6 + 8 * 2, DP
Example 4.14.28.13 MOV R1, 0x0200
Example 4.14.28.15 MOV *0x0200 * 2, R0
Transfer R5 to R0 Example
 Execution An + PH
Movaph Move With Adding PH
MOVAPHS, MOVTPH, MOVTPHS, MOVSPH, Movsphs
 MOVAPH, MOVTPH, MOVTPHS, MOVSPH, Movsphs
Movaphs Move With Adding PH
Execution + PH
Background. See .8 for more details
 Copy data memory byte pointed by R2 to accumulator A0
Movb Move Byte From Source to Destination
Copy value of unsigned src byte to dest byte
Movb A0, *R2
 Movb A0, 0xf2
Movb *R2, A0
Movb R2
 Movbs *0x0200, A2
Movbs Move Byte String from Source to Destination
TAG bit is set to bit 17th value
Movbs A2, *0x0200
 Adrs , *An
Movs Move String from Source to Destination
An ~ , adrs
Adrs , An ~
 Movs A1~, A1
MOVU, MOV, MOVT, MOVB, Movbs
Movs A2~
Movs A1, A1~
 MOVSPHS, MOVAPH, MOVAPHS, MOVTPH, Movtphs
Movsph
128
 Details
An second word PH MR contents of adrs
Assembly Language Instructions 129
Movsphs Move String With Subtract From PH
 MOVU, MOV, MOVT, MOVB, MOVBS, Movs
Movt
PC PC + w Flags Affected None Opcode
Available
 Copy the value pointed by R3 to MR
Movu Move Data Unsigned
TAG bit is set accordingly UM is set to
MOV, MOVB, MOVT, MOVBS, Movs
 Xxxxxx Xxxx00 Flag Bit
MR/SV An S APn
132
 MULR, MULAPL, MULSPL, MULSPLS, MULTPL, MULTPLS, Mulapl
14.38 MUL Multiply Rounded
MR * src PC PC + w Flags Affected
Accumulator pointer if specified
 Mulapl
Mulr Multiply Rounded With No Data Transfer
MR * src PC PC + Flags Affected
MULS, MUL, MULAPL, MULSPL, MULSPLS, MULTPL, Multpls
 PH,PL MR * src string
Length nS+2, where nS is the value in STR register
Assembly Language Instructions 135
Muls Multiply String With No Data Transfer
 MULAPLS, MULSPL, MULSPLS, MULTPL, Multpls
Mulapl Multiply and Accumulate Result
PH ,PL MR * src
Background. See .8 for more detail
 MR * src
Mulapls Multiply String and Accumulate Result
MULAPL, MULSPL, MULSPLS, MULTPL, Multpls
 Syntax Description Mulspl adrs
Mulspl Multiply and Subtract PL From Accumulator
Occuring in the background. See .8 for more details
MULSPLS, MULTPL, MULTPLS, MULAPL, Mulapls
 Syntax Description Mulspls adrs
Mulspls Multiply String and Subtract PL From Accumulator
From dest string
MULSPL, MULTPL, MULTPLS, MULAPL, Mulapls
 Multiply MR by data memory word, move PL to a n
Multpl Multiply and Transfer PL to Accumulator
~ , a n ~ , next a
Value of src. The 16 MSBs
 Example 4.14.46.2 Multpls A2, A2~
Multpls
Execution PH, PL MR * src PC PC + Flags Affected
MULTPL, MULAPL, MULAPLS, MULSPL, Mulspls
 Example 4.14.47.1 Negac A3~, A3, --A
Negac Two’s Complement Negation of Accumulator
Accumulator
NEGACS, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs
 NEGAC, SUB, SUBB, SUBS, ADD, ADDB, ADDS, NOTAC, Notacs
Assembly Language Instructions 143
Negacs Two’s Complement Negation of Accumulator String
Dest accumulator string
 Execution PC PC +
14.49 NOP No Operation
RPT
 Example 4.14.50.1 Notac A3~, A3, --A
Notac One’s Complement Negation of Accumulator
NOTACS, AND, ANDB, ANDS, OR, ORB, ORS, XOR, XORB, Xors
NEGAC, Negacs
 A3~
Notacs One’s Complement Negation of Accumulator String
Accumulator string
Negacs
 TFn bits in Stat register are set accordingly
14.52 or Bitwise Logical or
Accumulator pointers are allowed with some operand types
 148
ORB, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs
Or A0, *R0++R5
Or TF1, *R6+0x22
 OR, ORS, AND, ANDS, XOR, XORS, NOTAC, Notacs
14.53 ORB Bitwise or Byte
Or src
Accumulator is affected
 ORS A0, A0~, A0
14.54 ORS Bitwise or String
PC + w Flags Affected
OR, ORB, AND, ANDS, XOR, XORS, NOTAC, Notacs
 Address is multipled by 4 to get the actual port address
14.55 OUT
OUTS, IN, INS
 Port6 , An ~
Outs Output String to Port
Port6 specified in the instruction
OUT, IN, INS
 CALL, i.e., RET followed by a RET should not be allowed
14.57 RET Return From Subroutine CALL, Ccc
PC TOS
R7 R7 Flags Affected
 Sflag , Stag , Rtag
Rflag Reset Memory Flag
Example 4.14.58.2 Rflag *R6 +
 STAT.FM
Reset Fractional Mode Syntax
Resets the fractional mode. Clears FM bit of Stat
14.59 RFM
 Stat .OM
Rovm Reset Overflow Mode
Saturation output normal mode
Resets the overflow mode to zero
 After execution completes
14.61 RPT Repeat Next Instruction
If RPT adrs8 Load src to repeat counter
Load imm8 to repeat counter
 Rtag *R6+0x0003
Rtag Reset Tag
Stag , Rflag , Sflag
Rtag *R6+0x0002
 SXM
14.63 RXM Reset Extended Sign Mode
Assembly Language Instructions 159
STAT.XM
 160
Address flagadrs only accesses the 17 th bit
Sflag Set Memory Flag
Rflag , Stag , Rtag
 Set fractional mode. Set FM bit of Stat to
14.65 SFM Set Fractional Mode
Mode for signed fractional arithmetic
Assembly Language Instructions 161
 Shls
14.66 SHL Shift Left
PH , PL
Accumulator. Use Shlac for this purpose
 Example 4.14.67.2 Shlac A1~, A1, --A
Shlac Shift Left Accumulator
Its offset. LSB of result is set to zero
Shift accumulator A1 by one bit to the left
 Accumulators in the string
Shlacs Shift Left Accumulator String Individually
164
 Example 4.14.69.3 Shlapl A1, A1, ++A
Shlapl Shift Left with Accumulate
Example 4.14.69.1 Shlapl A0, *R4++R5
Shlapl A2, *R1++
 Shift data memory string left, add PL to a n
Shlapls Shift Left String With Accumulate
Shift a n ~ string left, addb PL to a n ~
 An~
Assembly Language Instructions 167
Shls Shift Left Accumulator String to Product
Execution PH, PL
 Example 4.14.72.3 Shlspl A1, A1, ++A
Shlspl Shift Left With Subtract PL
Example 4.14.72.1 Shlspl A0, *R4++R5
Shlspl A2, *R1++
 Shift RAM string left, subtract PL from An
Assembly Language Instructions 169
Shlspls Shift Left String With Subtract PL
NS+3 NR+3
 Example 4.14.74.3 Shltpl A1, A1, ++A
Shltpl Shift Left and Transfer PL to Accumulator
Example 4.14.74.1 Shltpl A0, *R4++R5
Shltpl A2, *R1++
 Shift the accumulator string A1 by nSV bits to the left
Shltpls Shift Left String and Transfer PL to Accumulator
Receives the same data as PH
SHLTPL, SHLAPL, SHLAPLS, SHLSPL, Shlspls
 Example 4.14.76.2 Shrac A1~, A1, ++A
Shrac Shift Accumulator Right
Register
Shift right one bit the accumulator A1
 Shltpls
Assembly Language Instructions 173
Shracs Shift Accumulator String Right
SHRAC, SHL, SHLS, SHLAPL, SHLAPLS, SHLSPL, SHLSPLS, Shltpl
 STAT.OM
Set Overflow Mode Syntax
Output DSP mode
Sovm
 RTAG, RFLAG, Sflag
Stag
Stag *0x401
 An ~ , An ~ , imm16 , next a
14.80 SUB Subtract
Dest, src , src1 , next a
An ~ , An , adrs , next a
 SUB R3, R5
Example 4.14.80.2 SUB A0, A0, 2, ++A
SUB A1, A1~, A1
SUB A3~, A3, *R4
 Syntax Description Subb a n, imm8
Subb Subtract Byte
Subtract 0x45 from accumulator A2 byte
Subtract 0xF2 from register R3 byte
 Subs Subtract Accumulataor String
Assembly Language Instructions 179
NR+2
 180
Subs A2, A2, A2~
Subs A2, A2~, A2
Subs A3~, A3~, PH
 RXM
14.83 SXM Set Extended Sign Mode
Sets extended sign mode status register Stat bit 0 to
Assembly Language Instructions 181
 See Also RET, IRET, CALL, C cc Example
Vcall Vectored Call
Push PC + 0x7F00
R7 R7 + Flags Affected
 TAG bit is set accordingly Src is flagadrs
14.85 XOR Logical XOR
XOR src For two operands
XOR src For three operands
 Example 4.14.85.1 XOR A1, A1, 0x13FF
XORB, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
Example 4.14.85.2 XOR A0, A0, 2, ++A
 Xorb Logical XOR Byte
Assembly Language Instructions 185
XOR, XORS, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
 Xors A2, A2~, A2
Xors Logical XOR String
Dest string
XOR, XORB, AND, ANDS, OR, ORS, ORB, NOTAC, Notacs
 ZAC A1~, ++A
14.88 ZAC Zero Accumulator
PC PC + Flags Affected ZF =
Zacs
 ZAC
Reset the content of offset accumulator string A1~ to zero
Zacs Zero Accumulator String
Zero the specified accumulator string
 Instruction Set Encoding
Assembly Language Instructions 189
Instruction Set Encoding
 190
 Assembly Language Instructions 191
 192
 Assembly Language Instructions 193
 194
 Assembly Language Instructions 195
 196
 Description True condition Not true condition
Assembly Language Instructions 197
 Instruction Set Summary
 An, An~
Pma16 , Rmod Assembly Language Instructions 199
An~, An~ , next a
An~, pma16
 MR , imm16 , next a
Adrs, a n~ , next a
~, adrs , next a
An ~, imm16 , next a
 Flagadrs† , TFn
Assembly Language Instructions 201
Adrs, TOS
STR, adrs
 Adrs An ~, An ~, imm16 , next a ~, a n~, a n , next a
~ , next a
~, a n~ , next a
~ , a n~
 An~, An~, An
An~, An~ , next a NR+3 Assembly Language Instructions 203
TFn, flagadrs NR+3 TFn, cc , Rx
An~, An~, pma16
 ~, a n~, PH
~, a n~
~, a n, a n~ , next a
~, a n, a n~
 Conditional on ZF=0 and SF=1 Not condition ZF≠ Or SF≠
Conditional on RCF=1 Not condition RCF=0
Conditional on RZF=0 and RCF=1 Not condition RZF≠ 0 or RCF≠
Conditional on RZF=1 Not condition RZF=0
 Instruction Set Summay
206Assembly Language Instructions
 MC = Pllm value+1 ⋅ 131.07 kHz
 208Assembly Language Instructions
 209
Language Instructions
Summay
 Instruction Set Summay 210Assembly Language Instructions
 Code Development Tools
 Introduction
 Code Development Tools
Pin IDC Connector top view looking at the board
 MSP50C6xx Development Tools Guidelines
MSP50C6xx Development Tools Guidelines
Categories of MSP50Cxx Development Tools
SDK50P614 kit of 15 MSP50P614s
 SPEECH-EVM†PC50C604†
Tools Definitions
 MSP50C6xx Development Tools Guidelines
 Software Tools-Definitions
 Documentation
MSP50C6xx Code Development Tools
System Requirements
 Hardware Tools Setup
 Green Target board power
Red MSPSCANPORTI/F power Yellow
 Assembler
Assembler
Assembler Directives
Examples
 #ELSE see #IF and #IFDEF
An assembly language program
 #ENDIF
#IF expression Do something here
#ELSE
Do other things here
 #IFNDEF symbol
Example #IFDEF symbol
 Assembler
 Foreword
Compiler
Compiler
 External References
Variable Types
Type Name Mnemonic Range Size in Bytes Example
 With Arguments
Defines a replacement string for a given string
Directives
Without Arguments
 See #if directive
Include Files
 #define STRLENGTHi Major Differences between C and C
 Initialization values are stored in program memory
Function Prototypes and Declarations
Initializations
RAM Usage
 String Functions
String Functions
Operator can take the following values predefined constants
 An example of the use of xferconst is
Constant Functions
 Signed comparison of a and b. a is in A0, b is in A0~
Implementation Details
Comparisons
This section is C- specific
 Ugt
Assembly Vector
Unsigned comparison of a and b. a is in A0, b is in A0~
Ult
 Low Address High Address
Division
Function Calls
Stack frame has the following structure
 On RET
Programming Example
Cmmfunc bidonint i1,char *i2 is valid, but
On Call
 #include cmmmacr.h
 Reserved
Programming Example, C -- With Assembly Routines
 Implementation Details
 R7Param
 Addb R7,2
 To C function return in roncoreturn
 OldR5 Return Addr Param R7,R5 Stack data
 Param R7,R5 Stack data Before call Parameter
 Return Addr Param Stack data
 To ASM function return
Efficiency
Efficiency
 Efficiency
 Example 5-1. First Project
Real Time Clock Example
 Jrtc.rpj Hmodules
 MAINRAM.IRX
Allocated by changing
 Efficiency
 CMM1.ASM
 Allocated as follows
Sixth file, cmm1ram.asm, allocates memory for cmm1.asm
 MAIN.CMM
 Example 5-2. Second Project C-- With Speech
 Isr Tim2isr.asm dacisr.asm J tim1isr.asm
Celp Celp.irx
Util.obj
Dspvar.irx dsputil.asm getbits.asm speak.asm speak.irx
 Dsp
Tens.qfm
Melp
Ampm.qfm
 Ramendcustomer Ramstartcustomer
 New C-- callable functions were declared global
Assembly routines that will be called are declared external
Clock will need to say
 Cmmfunc speakHours
 Example 5-3. Third Project C-- with an LCD
 Lcd Lcd.asm Lcd.irx
Melp.irx Melp.obj
Celp Ampm.qfm Days.qfm Ones.qfm Teens.qfm
 External lcdsetio external lcdinit
 Case
 Efficiency
 Beware of Stack Corruption
Beware of Stack Corruption
 Reported Bugs With Code Development Tool
Reported Bugs With Code Development Tool
 Applications
 Application Circuits
Application Circuits
 Applications6-3
∝ F 22 pF
MSP50P614 only 100 kΩ
3300 pF
 Initializing the MSP50C6xx
Initializing the MSP50C6xx
 Applications6-5
File init.asm
 JNZ Itsacpart Itsappart
 Applications6-7
 Getting Started
TI-TALKS Example Code
TI-TALKS Example Code
 Applications6-9
RAM Overlay
Creating a New Project
RAM Overlay
 Adding Customer Variables
RAM Overlay
 Common Problems
Page
 Customer Information
 Die Bond-Out Coordinates
Mechanical Information
Package Information
 Customer Information
Signal and Pad Descriptions for the MSP50C614
 Signal and Pad Descriptions for the MSP50C605
 Signal and Pad Descriptions for the MSP50C601
 Signal and Pad Descriptions for the MSP50C604
 Pin QFP Mechanical Information
 13 NOM
 Extra pin 3 4 5 6 7 8 9 10 11 12 13 Bottom View
13 12 11 10 9 8 7 6 5 4 3 2
 Bottom view
Bottom View of 120-Pin PGA Package of the MSP50P614
 Customer Information Fields in the ROM
Customer Information Fields in the ROM
0x0006 Device number 0x0614
 Software Design Hardware Design
Speech Specification
Speech Development Cycle
Device Production Sequence
 Device Production Sequence
 Code Letter PJM Loopin 100-Pin QFP
Ordering Information
New Product Release Forms Nprf
6xx
 New Product Release Forms Nprf
 Approval of Prototypes and Authorization to Start Production
 NEW Product Release Form for MSP50C604 Option Selection
 New Product Release Forms Nprf
 NEW Product Release Form for MSP50C605 Option Selection
 New Product Release Forms Nprf
 NEW Product Release Form for MSP50C601 Option Selection
 New Product Release Forms Nprf
 Topic
Additional Information
 Additional Information
Additional Information