Xilinx ML310 manual DDR Memory, Board Hardware

Board Hardware

R

X8

IIPro FPGA I/O can be configured to use different IO standards such as SSTL2 as required on the DDR DIMM interface. Please review the ML310 Virtex-II Pro data sheet for more information regarding I/O standards.

Figure 2-3shows the top-level clocking for the ML310 board.

OSC 33MHz

X7

OSC 156.25 MHz

X9

OSC 125MHz

SYACE_FPGA_CLK

SYSACE LCD

PM_CLK_TOP

J20

LVDS_CLK_LOC_P

LVDS_CLK_LOC_N

J17 USER_SMA_CLK

J21

	7P	6S	5P	4S
PM IO	12	BANK 0
2.5V			2.5V
LVDS	(6 LVDS)
		DCM		DCM
		X0Y1		X1Y1

BANK 7

DDR Note: 2.5V DIMM All 3 DDR

64 bit Clock nets 256MB are length

matched

DDR_CLK

DDR_CLKB

BANK 6
2.5V
FB	DCM		DCM
CLK
	X0Y0		X1Y0
DDR_	BANK 5
		2.5V
7S	6P	5S	4P

LVDS CLK LOC N	LVDS CLK LOC P	USER CLKSYS	DDR_CLK_FB
			(notused)

OSC

X6

SYACE_FPGA_CLK

LEDs

IIC

UART

PM IO

3V

26

SYS_CLK

LVDS_CLK_EXT_N

(user_clk_pci)

LVDS_CLK_EXT_P

PCI_P_CLK5

Note:

All 5 PCI

3P

2S

1P

0S

PCI_P_CLK1

Clock nets

thru

are length

BANK 1

PCI_P_CLK4 matched

3.0V

DCM

DCM

X2Y1

X03Y1

PCI

BANK 2

BUS

3.0V

3.0V

BANK 3

2.5V

72

PM IO

(36 LVDS)

2.5V

DCM

DCM

LVDS

X2Y0

X3Y0

BANK 4

2.5V

3S

2P

1S

0P

LVDS_CLK_EXT_P

LVDS_CLK_EXT_N

PM_CLK_BOT

8

6

MGTs

(3 LVDS)

(to FPGA)

CPU

TRACE

SPI

PM IO

DEBUG

2.5V

X10

OSC 100MHz

PM2

PM1

Figure 2-3:Top-Level Clocking

DDR Memory

DDR DIMM

The ML310 includes a registered 256MB PC3200 Double Data Rate (DDR) Dual Inline Memory Module (DIMM) with an industry standard 184-pin count. The DDR DIMM is commercially available from Wintec Industries as part number W4F232726HA-5Q. The associated datasheet is provided on the ML310 CDROM. The DDR DIMM is manufactured using nine Infineon HYB25D256800BT-5, 32Mx8 DDR SDRAM devices with 13-row address lines, 10-column address lines, and 4 bank select lines. Read and write access to the Infineon devices is programmable in burst lengths of 2, 4, or 8 column locations. The memory module inputs and outputs are compatible with SSTL2 signaling. Serial Presence Detect (SPD) using an SMBus interface to the DDR DIMM is also supported. Please refer to section “IIC/SMBus Interface” for more details on accessing the DIMM module’s SPD EEPROM.

ML310 User Guide	www.xilinx.com	21
UG068 (v1.01) August 25, 2004	1-800-255-7778