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Chapter 2: ML310 Embedded Development Platform

Arbiter IP. Please see the EDK Processor IP Reference Guide for more information about the EDK IP mentioned in this section.

The FPGA is responsible generating the PCI RST signal as well as the PCI CLK signal. The FPGA fabric is used to generate six PCI Clocks that drive each of the PCI devices/slots shown in the Figure 2-11. All six PCI Clock outputs are length matched. Since the FPGA generates all PCI Clocks, the downstream PCI devices have no clock input prior to or during FPGA configuration therefore, PCI Reset should be de-asserted after the PCI CLK has stabilized. Please review the PCI Local Bus Specification, Revision 2.2 for more detailed information.

The on-board 33MHz/32 bit PCI Bus is connected to three fixed PCI devices that are part of the ML310 board. These devices are listed below and more information on the devices can be found in the following sections as well their data sheets on the ML310 CDROM

Texas Instruments, TI2250, PCI-to-PCI Bridge

Intel, GD82559, 10/100 PCI Ethernet NIC.

Ali, M1535D+, PCI South Bridge

In addition to the three fixed PCI devices, there are a total of four 33MHz/32 Bit PCI slots available for use. For more information on the PCI slot pinouts, refer to the PCI Local Bus Specification, Revision 2.2 and the ML310 schematics.

2 - 3.3V Keyed PCI Add In Card Slots (P5 and P3)

2 - 5.0V Keyed PCI Add In Card Slots (P6 and P4)

Note: The 5.0V PCI slots differ from the 3.3V slots. See the Important Instructions sheet (PN 0402263) packaged with the ML310 kit before using Universal PCI add-in cards with the ML310 board.

Figure 2-11shows the connectivity of the PCI bus and PCI devices. For more information on the PCI slot pinouts, refer to the PCI 2.2 Specification or review the ML310 schematics. The 5.0V PCI slots differ from the 3.3V slots. See the Important Instructions sheet

(PN 0402263) packaged with the ML310 kit before using Universal PCI add-in cards with the ML310 board.

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ML310 User Guide

 

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Xilinx manual ML310 Embedded Development Platform