Xilinx ML310 manual 14SMBus and IIC Block Diagram

Board Hardware

R

Table 2-14shows a block diagram of the FPGA in relation to the SMBus accelerator and the IIC bus.

Note: Either the XC2VP30 or the ALi M1535D+ can master the IIC bus but not simultaneously

U37

Virtex-II Pro

FPGA

XC2VP30

IIC Bus

U15

PCI Bus

ALi

Southbridge

M1535 D+

U27
SMBUS
Accelerator
LTC1694
U20
Voltage		Temperature
Temp		VCC12V_P
Monitor		VCC5V
		VCC2V5
ADDR:		VVCC3_PCI
0x5C		VCC1V5
LM87
U22
RTClock
ADDR:
0xA2
RTC8566
U21
EEPROM
ADDR:
0xA0
24LC64
P7
SPD	Note: Located on
EEPROM	DDR DIMM P7

Figure 2-14:SMBus and IIC Block Diagram

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UG068 (v1.01) August 25, 2004	1-800-255-7778