Xilinx ML310 manual ALi South Bridge Interface, M1535D+, U15, Device Name Bus

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Chapter 2: ML310 Embedded Development Platform

Table 2-11describes how the Primary PCI Bus interrupts are connected on the ML310 board along with each devices IDSEL, REQ/GNT, PCI Clocks and DeviceID/Vendor ID information.

Table 2-11:3.3V Primary PCI Bus Information

	Device	Vendor					FPGA
Device Name			Bus	DEV	IDSEL		PCI	INTR
	ID	ID				REQ
							CLK
PCI Slot 5	N/A	N/A	0	5	AD21	0	0	A,B,C,D
PCI Slot 3	N/A	N/A	0	6	AD22	1	1	B,C,D,A
U11, Enet Mac	0x1229	0x8086	0	7	AD23	2	2	C
U15, ALI SB	0x1533	0x10B9	0	2	AD18	3	3	INT,NMI
U15, ALi Pwr Mgt	0x7101	0x10B9	0	12	AD28	3	3	INT,NMI
U15, ALI IDE	0x5299	0x10B9	0	11	AD27	3	3	INT,NMI
U15, ALi Audio	0x5451	0x10B9	0	1	AD17	3	3	INT,NMI
U15, Ali Modem	0x5457	0x10B9	0	3	AD19	3	3	INT,NMI
U15, ALi USB#1	0x5237	0x10B9	0	15	AD31	3	3	INT,NMI
U15, ALi USB#2	0x5237	0x10B9	0	10	AD26	3	3	INT,NMI
U32, PCI-PCI Brg	0xAC23	0x104C	0	9	AD25	4	4	N/A
U37, XC2VP30	0x0300	0x10EE	0	8	AD24	Int.	5	N/A

Table 2-12describes how the Secondary PCI Bus interrupts are connected on the ML310 board along with each devices IDSEL, REQ/GNT, PCI Clocks and DeviceID/Vendor ID information.

Table 2-12:5.0V Secondary PCI Bus Information

Device Name	Device	Vendor	Bus	DEV	IDSEL		Bridge	INTR
	ID	ID				REQ	CLK
PCI Slot 6	N/A	N/A	1	2	AD18	0	0	A,B,C,D
PCI Slot 4	N/A	N/A	1	3	AD19	1	1	B,C,D,A
U32, PCI-PCI Brg	N/A	N/A	N/A	7	N/A	Int.	4	N/A

ALi South Bridge Interface, M1535D+, U15

The ALi M1535D+ South Bridge augments the ML310 with many of the basic features found on legacy Personal Computers (PCs). These basic PC features are only accessible over the PCI Bus as this is the only way to access the ALI M1535D+. A brief description of the ALi M1535D+ features employed on the ML310 board is discussed below. Please review the ALi M1535D+ Data sheets, located on the ML310 CDROM, for more detailed information.

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