31 PM1 Pinout | Xilinx ML310 specification

High-Speed I/O

Table 2-31: PM1 Pinout (Continued)

R

	PM1 Pin	FPGA Pin	Pin Description	ML310 Schematic Net	FPGA Bank
	PM1 Pin	FPGA Pin	Pin Description	ML310 Schematic Net	VCCO
					VCCO
	D4	G25	IO_L02N_7	PM_IO_85	2.5V

	D5	A8	IO_L44N_1	PM_IO_3V_21	3V

	D6	B8	IO_L44P_1	PM_IO_3V_20	3V

	D7	D7	IO_L08P_1	PM_IO_3V_8	3V

	D8	F9	IO_L07P_1	PM_IO_3V_6	3V

	D9	E8	IO_L03P_1	PM_IO_3V_2	3V

	D10	D8	IO_L38P_1	PM_IO_3V_14	3V

	D11	D17	IO_L67P_0	PM_IO_78	2.5V

	D12	E17	IO_L67N_0	PM_IO_79	2.5V

	D13	A27	TXNPAD4	TXNPAD4_A27

	D14	A26	TXPPAD4	TXPPAD4_A26

	D15	A14	TXNPAD7	TXNPAD7_A14

	D16	A13	TXPPAD7	TXPPAD7_A13

	D17	AK4	RXNPAD16	RXNPAD16_AK4

	D18	AK5	RXPPAD16	RXPPAD16_AK5

	D19	AK17	RXNPAD19	RXNPAD19_AK17

	D20	AK18	RXPPAD19	RXPPAD19_AK18

	F1	J24	IO_L05P_7	PM_IO_88	2.5V

	F2	J23	IO_L05N_7	PM_IO_89	2.5V

	F3	H10	IO_L09P_1	PM_IO_3V_10	3V

	F4	H9	IO_L06P_1	PM_IO_3V_4	3V

	F5	C8	IO_L38N_1	PM_IO_3V_15	3V

	F6	F7	IO_L02P_1	PM_IO_3V_0	3V

	F7	G12	IO_L45N_1	PM_IO_3V_23	3V

	F8	G10	IO_L09N_1	PM_IO_3V_11	3V

	F9	B16	GCLK6S	PM_CLK_TOP	2.5V

	F10	NC	NC	NC	NC

	F11	F15/AH15	GCLK3P/1S	LVDS_CLKEXT_N	2.5V

	F12	G15/AJ15	GCLK2S/0P	LVDS_CLKEXT_P	2.5V

	F13	A20	TXNPAD6	TXNPAD6_A20

	F14	A19	TXPPAD6	TXPPAD6_A19

	F15	A7	TXNPAD9	TXNPAD9_A7

	F16	A6	TXPPAD9	TXPPAD9_A6

ML310 User Guide	www.xilinx.com	67
UG068 (v1.01) August 25, 2004	1-800-255-7778

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Xilinx ML310 manual 31 PM1 Pinout

Contents

UG068 v1.01 August 25 ML310 User Guide ML310 User Guide Version Revision ML310 User Guide UG068 v1.01 August 25 UG068 v1.01 August 25 Table of Contents UG068 v1.01 August 25 Additional Resources Manual Contents Typographical Conventions Handbook Online Document Chapter Virtex-II Pro Summary of Virtex-II Pro Features RocketIO 3.125 Gb/s Transceivers PowerPC 405 Core Virtex-II Pro Virtex-II Fpga Fabric Introduction to Virtex-II Pro, ISE, and EDK Foundation FeaturesFoundation ISE Design Entry Synthesis Implementation and ConfigurationFoundation ISE Board Level Integration Embedded Development Kit Overview ML310 Embedded Development Platform ML310 Board ML310 Embedded Development Platform Overview Features Clock Generation Board Hardware Board Hardware DDR Memory DDR Memory Expansion DDR SignalingU37 DDRA2 DDRDQS02 DDRDQ31 RS-232 on the ML310 Signaling Standards of RS-232Serial Port Fpga Uart Introduction to Serial Ports Board Bring-Up System ACE CF Controller XC2VP30 Connectivity Non-Volatile Storage 6JTAG Connections to the XC2VP30 and System ACE Jtag Connection to XC2VP30 Gpio LEDs and LCD System ACE Jtag Configuration InterfaceParallel Cable IV Interface 8LEDs and LCD Connectivity U37 Name U36 UCF Signal Name Translator U37 J13 U35Gpio LED Interface Gpio LCD Interface CPU Debug Description CPU Debug and CPU TraceBuffer U33 J13 9Combined Trace/Debug Connector Pinout PCI Bus CPU Debug Connector PinoutCPU Debug Connection to XC2VP30 ML310 Embedded Development Platform 11 PCI Bus and Device Connectivity Pciinta Pciintb Pciintc Pcipar Pcippar Pcirstn Pciprstn 125.0V Secondary PCI Bus Information Device Name Vendor ALi South Bridge Interface, M1535D+, U15113.3V Primary PCI Bus Information Device Vendor Device Name Bus 12ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1 Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 System Management Bus SMBus GPIO, connector J517Type of Gpio Available on Header J5 ALi Gpio Types Number AC97 Audio 19Audio Jacks, J1 and J2 Signal name Description Flash ROM, U4 PS/2 Keyboard/Mouse Interface, connector P2 Intel GD82559 Ethernet Controller Intel GD82559, U11, 10/100 Ethernet Controller IIC/SMBus on ML310 Board IIC/SMBus SignalingIIC/SMBus Interface Introduction to IIC/SMBus 22shows the Fpga connections to all SMBus and IIC devices 14SMBus and IIC Block Diagram Serial Peripheral Interface SPI SPI Signaling SPI Addressing Push Buttons, Switches, Front Panel Interface and JumpersPush Buttons CPU Reset, SW2 System ACE Configuration Dipswitch, SW3 16SW3 SysACE CFG Switch Detail Front Panel Interface Connector, J23 SYACECFGA0 Voltage Jumper JumpersJ10 J11 Coupling MGT Bref Clock Selection Jumpers, J20 and J21 ATX Power Distribution and Voltage Regulation 17ATX Power Distribution and Voltage Regulation 18Voltage Monitor High-Speed I/O High-Speed I/O 19Personality Module Connected to ML310 Board ML310 PM Connectors PM2 Connector PM1 Connector Adapter Board PM Connectors ML310 PM Utility PinsContact Order PM1 User I/O ML310 PM User I/O PinsPM1 Power and Ground PM2 Power and Ground RXPPAD4 RXPPAD4A25 31 PM1 Pinout RXPPAD21 RXPPAD21AK25 ML310 PM2 User I/O 32 PM2 Pinout AA5