Xilinx ML310 manual DDRDQS02

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Chapter 2: ML310 Embedded Development Platform

Table 2-1:Connections from FPGA to DIMM Interface, P7

UCF Signal Name	XC2VP30 Pin	Schem Signal Name	DIMM
	(U37)		(P7)
ddr_dqs[5]	M29	DDR_DQS02	25
ddr_dqs[6]	H29	DDR_DQS01	14
ddr_dqs[7]	F29	DDR_DQS00	5
ddr_dq[0]	AG28	DDR_DQ63	179
ddr_dq[1]	AG26	DDR_DQ62	178
ddr_dq[2]	AE26	DDR_DQ61	175
ddr_dq[3]	AD26	DDR_DQ60	174
ddr_dq[4]	AH27	DDR_DQ59	88
ddr_dq[5]	AH26	DDR_DQ58	87
ddr_dq[6]	AF25	DDR_DQ57	84
ddr_dq[7]	AD25	DDR_DQ56	83
ddr_dq[8]	AF28	DDR_DQ55	171
ddr_dq[9]	AD28	DDR_DQ54	170
ddr_dq[10]	AB25	DDR_DQ53	166
ddr_dq[11]	AB26	DDR_DQ52	165
ddr_dq[12]	AF27	DDR_DQ51	80
ddr_dq[13]	AD27	DDR_DQ50	79
ddr_dq[14]	AC25	DDR_DQ49	73
ddr_dq[15]	AC26	DDR_DQ48	72
ddr_dq[16]	AC27	DDR_DQ47	162
ddr_dq[17]	AC28	DDR_DQ46	161
ddr_dq[18]	AA26	DDR_DQ45	155
ddr_dq[19]	Y26	DDR_DQ44	153
ddr_dq[20]	AB27	DDR_DQ43	69
ddr_dq[21]	AB28	DDR_DQ42	68
ddr_dq[22]	AA25	DDR_DQ41	64
ddr_dq[23]	Y27	DDR_DQ40	61
ddr_dq[24]	W28	DDR_DQ39	151
ddr_dq[25]	W25	DDR_DQ38	150
ddr_dq[26]	V27	DDR_DQ37	147
ddr_dq[27]	V25	DDR_DQ36	146
ddr_dq[28]	W27	DDR_DQ35	60
ddr_dq[29]	W26	DDR_DQ34	57
ddr_dq[30]	V28	DDR_DQ33	55
ddr_dq[31]	V26	DDR_DQ32	53

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	1-800-255-7778	UG068 (v1.01) August 25, 2004