Xilinx ML310 - page 3

UG068 (v1.01) August 25, 2004 www.xilinx.com ML310 User Guide

1-800-255-7778

ML310 User Guide

UG068 (v1.01) August 25, 2004

The following table shows the revision history for this document..

Version Revision

08/15/04 1.0 Initial Xilinx release.

08/25/04 1.01 Added SysACE CFGADDR details.

Contents

Main ML310 User Guide www.xilinx.com UG068 (v1.01) August 25, 2004 1-800-255-7778 Page Page Table of Contents Preface: About This Manual Chapter 1: Introduction to Virtex-II Pro, ISE, and EDK Virtex-II Pro Foundation ISE Embedded Development Kit High-Speed I/O Preface About This Manual Manual Contents Additional Resources Conventions Typographical Online Document Page Chapter 1 Introduction to Virtex-II Pro, ISE, and EDK Virtex-II Pro Summary of Virtex-II Pro Features PowerPC 405 Core RocketIO 3.125 Gb/s Transceivers Virtex-II FPGA Fabric Foundation ISE Foundation Features Design Entry Synthesis Implementation and Configuration Board Level Integration Embedded Development Kit Chapter 2 ML310 Embedded Development Platform Overview Page Features Board Hardware Clock Generation Figure 2-3: Top-Level Clocking DDR Memory DDR DIMM DDR Signaling DDR Memory Expansion Page Page ML310 User Guide www.xilinx.com 25 UG068 (v1.01) August 25, 2004 1-800-255-7778 UCF Signal Name XC2VP30 Pin (U37) Schem Signal Name DIMM Serial Port FPGA UART Introduction to Serial Ports Signaling Standards of RS-232 RS-232 on the ML310 System ACE CF Controller Board Bring-Up Non-Volatile Storage XC2VP30 Connectivity JTAG JTAG Connection to XC2VP30 J9 PC4 System ACE XC2VP30 Parallel Cable IV Interface GPIO LEDs and LCD GPIO Figure 2-8: LEDs and LCD Connectivity LCD ML310 User Guide www.xilinx.com 31 GPIO LED Interface GPIO LCD Interface CPU Debug and CPU Trace CPU Debug Description Page CPU Debug Connector Pinout CPU Debug Connection to XC2VP30 PCI Bus Page Tabl e 2-10 shows the connections for the PCI controller. PCI-to-PCI Bridge TI2250 U11 U15 ALi Southbridge Page Table 2-10: PCI Controller Connections (Continued) UCF Signal Name XC2VP30 Pin (U37) Description ALi South Bridge Interface, M1535D+, U15 ML310 User Guide www.xilinx.com 41 ALi M1535D+ supports the following features: FPGA Figure 2-12: ALi South Bridge Interface, M1535D+, U15 Parallel Port Interface, connector assembly P1 Serial Port Interface, connector assembly P1 USB, connector assembly J3 IDE, connectors J15 and J16 GPIO, connector J5 System Management Bus (SMBus) AC97 Audio PS/2 Keyboard/Mouse Interface, connector P2 Flash ROM, U4 Intel GD82559, U11, 10/100 Ethernet Controller Intel GD82559 Ethernet Controller IIC/SMBus Interface Introduction to IIC/SMBus IIC/SMBus Signaling IIC/SMBus on ML310 Board FPGA XC2VP30 Page ML310 User Guide www.xilinx.com 51 Figure 2-14: SMBus and IIC Block Diagram Serial Peripheral Interface (SPI) SPI Signaling SPI Addressing Push Buttons, Switches, Front Panel Interface and Jumpers Push Buttons System ACE Reset, SW1 CPU Reset, SW2 System ACE Configuration Dipswitch, SW3 Front Panel Interface Connector, J23 Page Jumpers MGT VTRX Termination Voltage Jumpers, J10 and J11 MGT BREF Clock Selection Jumpers, J20 and J21 System ACE Configuration Mode Jumper, J14 JTAG Source Select Jumper, J19 ATX Power Distribution and Voltage Regulation ML310 User Guide www.xilinx.com 59 Note: Figure 2-17: ATX Power Distribution and Voltage Regulation Figure 2-18: Voltage Monitor High-Speed I/O ML310 PM Connectors Host Board ConnectorAdapter Board Connector Personality Module ML310 Board PM1 Connector Plastic Divider PM2 Connector Copper Pins Adapter Board PM Connectors ML310 PM Utility Pins Contact Order Plastic Housing Copper Pins PM1 Power and Ground PM2 Power and Ground ML310 PM User I/O Pins PM1 User I/O Table 2-31: PM1 Pinout (Continued) PM1 Pin FPGA Pin Pin Description ML310 Schematic Net FPGA Bank High-Speed I/O Table 2-31: PM1 Pinout (Continued) PM1 Pin FPGA Pin Pin Description ML310 Schematic Net FPGA Bank ML310 PM2 User I/O High-Speed I/O Table 2-32: PM2 Pinout (Continued) PM2 Pin FPGA Pin Pin Description ML310 Schematic Net FPGA Bank