Board Hardware

R

a UART usable with any member of the Virtex-II Pro device family. Please review the EDK Processor IP Reference Guide for more details.

The RS-232 port directly connected to the XC2VP30 is accessible by a 10 pin header(J4). An RS-232 mini-cable adapter included with the ML310 converts J4, 10 pin header, to a DB9 male connector. The adapter is a standard DTK/Intel IDC-10 to DB9 Male. The FPGA RS- 232 port on the ML310 is wired as a DTE and meets the EIA/TIA-574standard

Figure 2-5shows the RS-232 connectivity from the XC2VP30 to the DTK adapter.

.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

USE A DTK-PINOUT IDC10

 

 

 

 

 

 

 

J4

TO DB9 PLUG CABLE.

 

 

 

 

 

 

 

 

 

 

 

 

U37

U7

 

 

 

1

 

2

 

1

CD

UART0_TXD

11 DIN1

 

14

COM0_TXD_N

 

 

 

DSR

DOUT1

3

 

4

6

 

UART0_RTS_N

10 DIN2

DOUT2

7

COM0_RTS

 

 

2

RX

UART0_RXD

12 ROUT1

RIN1

13

COM0_RXD_N

 

 

RTS

7

 

UART0_CTS_N

9 ROUT2

RIN2

8

COM0_CTS

5

 

6

 

3

TX

 

 

 

 

 

7

 

8

CTS

8

 

 

 

 

 

VCC3V3

 

 

4

DTR

 

 

 

 

 

 

 

RI

 

 

 

 

 

9

 

10

9

 

 

 

 

 

 

 

 

5

GND

 

1 C1+

VCC16

 

 

 

 

 

 

 

 

 

 

 

 

 

C330

 

 

 

C326

HEADER2X5

 

 

 

0.1UF

 

 

 

0.1UF

 

 

 

 

RS232 DTE PINOUT

 

3 C1-

 

2

 

 

 

 

 

CONNECTS TO PC WITH

 

V+

 

 

 

 

 

F/F NULL MODEL CABLE.

 

4 C2+

 

6

VCC3V3

 

 

 

 

 

 

V-

 

 

 

 

 

 

 

C331

 

 

 

C327

 

 

 

 

 

 

0.1UF

 

 

 

0.1UF

C313

 

 

 

 

 

 

 

 

 

 

0.1UF

 

 

 

 

 

 

5 C2-

GND15

 

 

 

 

 

 

 

XC2VP30

MAX3232

 

 

 

 

 

 

 

 

 

 

 

 

 

 

UG068_5_32_080204

 

 

 

 

 

Figure 2-5:FPGA UART and RS-232 Connectivity

Table 2-3shows the RS-232 connections to the XCV2VP30 FPGA.

Table 2-3:FPGA RS-232 Connections

UCF Signal

XC2VP30 Pin

Schem Signal

10 pin Header

DTK Adapter

Name

(U37)

Name

(J4)

(DB9)

 

 

 

 

 

uart1_ctsn

B10

UART0_CTS

6

8

 

 

 

 

 

uart1_rtsn

G14

UART0_RTS

4

7

 

 

 

 

 

uart1_sin

F14

UART0_RXD

3

2

 

 

 

 

 

uart1_sout

F12

UART0_TXD

5

3

 

 

 

 

 

System ACE CF Controller

Board Bring-Up

System ACE is the primary means of configuring the XC2VP30 on the ML310 board.Configuration of XC2VP30 is accomplished using the JTAG interface. System ACE sits between the JTAG connector and the XC2VP30, and passes the JTAG signals back and forth between the two. However, when System ACE is configuring the XC2VP30, it takes control of the JTAG signals in order to configure the XC2VP30.

ML310 User Guide

www.xilinx.com

27

UG068 (v1.01) August 25, 2004

1-800-255-7778

 

Page 27
Image 27
Xilinx ML310 manual System ACE CF Controller, Board Bring-Up