Texas Instruments TMS320F2808 manuals
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Texas Instruments TMS320F2808 Specifications
144 pages 1.4 Mb
Data Manual2 Contents5 TMS320C2801, TMS320F28016, TMS320F28015List of Figures 6 TMS320F2809, TMS320F2808, TMS320F2806TMS320C2801, TMS320F28016, TMS320F28015 7 List of TablesTMS320F2809, TMS320F2808, TMS320F2806 9 Digital Signal Processors1 F280x, F2801x, C280x DSPs 15 TMS320C2801, TMS320F28016, TMS320F28015Figure 2-2. TMS320F2806 100-Pin PZ LQFP (Top View)TMS320C2801 TMS320F28016 TMS320F28015Copyright 20032009, Texas Instruments Incorporated Introduction 15 16 TMS320C2801, TMS320F28016, TMS320F28015A. On the C280x devices, the VDD3VFL pin is VDDIO. TMS320C2801 TMS320F28016 TMS320F28015 Figure 2-3. TMS320F2802, TMS320F2801, TMS320C2802, TMS320C2801 100-Pin PZ LQFP (Top View)16 Introduction A. CANTXA (pin 7) and CANRXA (pin 6) pins are not applicable for the TMS320F28015. 17 Figure 2-4. TMS320F2801x 100-Pin PZ LQFP (Top View)Copyright 20032009, Texas Instruments Incorporated Introduction 17 18 4D 21 3 C B A E K H G F J 5 76 98 10 Bottom View 18 Introduction 19 2.2 Signal Descriptions24 Some peripheral functions may not be available in TMS320F2801x devices. See Table 2-2 for details.Protected by the code-security module. 25 3 Functional Overview28 Figure 3-4. F2806 Memory Map29 Figure 3-5. F2802, C2802 Memory MapSPRS230LOCTOBER 2003REVISED DECEMBER 2009 30 Figure 3-6. F2801, F28015, F28016, C2801 Memory Map31 Table 3-1. Addresses of Flash Sectors in F2809Table 3-2. Addresses of Flash Sectors in F2808 Table 3-3. Addresses of Flash Sectors in F2806, F2802 34 3.2 Brief Descriptions 3.2.1 C28x CPU3.2.2 Memory Bus (Harvard Bus Architecture) 3.2.3 Peripheral Bus 35 3.2.4 Real-Time JTAG and Analysis3.2.5 Flash 3.2.6 ROM 3.2.7 M0, M1 SARAMs 36 3.2.8 L0, L1, H0 SARAMs3.2.9 Boot ROM 37 3.2.10 Security38 3.2.11 Peripheral Interrupt Expansion (PIE) Block3.2.12 External Interrupts (XINT1, XINT2, XNMI) 3.2.13 Oscillator and PLL 3.2.14 Watchdog 3.2.15 Peripheral Clocking 3.2.16 Low-Power Modes 39 3.2.17 Peripheral Frames 0, 1, 2 (PFn)3.2.18 General-Purpose Input/Output (GPIO) Multiplexer 3.2.19 32-Bit CPU-Timers (0, 1, 2) 3.2.20 Control Peripherals 40 3.2.21 Serial Port Peripherals3.3 Register Map 42 3.4 Device Emulation Registers3.5 Interrupts 45 3.5.1 External InterruptsTable 3-14. External Interrupt Registers 46 3.6 System ControlFigure 3-9. Clock and Reset Domains 47 3.6.1 OSC and PLL BlockFigure 3-10 shows the OSC and PLL block on the 280x. 51 3.6.2 Watchdog Block52 3.7 Low-Power Modes Block53 4 Peripherals4.1 32-Bit CPU-Timers 0/1/2 55 .79 Figure 4-14 is a block diagram of the SPI in slave mode.A. SPISTE is driven low by the master for a slave device. Figure 4-14. SPI Module Block Diagram (Slave Mode) 80 4.10 Inter-Integrated Circuit (I2C)82 4.11 GPIO MUX86 5 Device Support93 6 Electrical Specifications133 7 Migrating From F280x Devices to C280x Devices134 8 Revision History135 9 Mechanical Data141 MECHANICAL DATAGGM (SPBGAN100) PLASTIC BALL GRID ARRAY 143 MECHANICAL DATA
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