Texas Instruments TMS320C2802 SPI Master Mode External Timing Clock Phase = 0 1 2 3 4

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

www.ti.com					SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009
		Table 6-34. SPI Master Mode External Timing (Clock Phase = 0)(1) (2) (3) (4) (5)
			SPI WHEN (SPIBRR + 1) IS EVEN OR		SPI WHEN (SPIBRR + 1) IS ODD AND
NO.			SPIBRR = 0 OR 2		SPIBRR > 3		UNIT
			MIN	MAX	MIN	MAX
1	tc(SPC)M	Cycle time, SPICLK	4tc(LCO)	128tc(LCO)	5tc(LCO)	127tc(LCO)	ns
	tw(SPCH)M	Pulse duration, SPICLK high	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M – 0.5tc(LCO) – 10	0.5tc(SPC)M – 0.5tc(LCO)
2		(clock polarity = 0)					ns
	tw(SPCL)M	Pulse duration, SPICLK low	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M – 0.5tc(LCO) – 10	0.5tc(SPC)M – 0.5tc(LCO)
		(clock polarity = 1)
	tw(SPCL)M	Pulse duration, SPICLK low	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M + 0.5tc(LCO) – 10	0.5tc(SPC)M + 0.5tc(LCO)
3		(clock polarity = 0)					ns
	tw(SPCH)M	Pulse duration, SPICLK high	0.5tc(SPC)M – 10	0.5tc(SPC)M	0.5tc(SPC)M + 0.5tc(LCO) – 10	0.5tc(SPC)M + 0.5tc(LCO)
		(clock polarity = 1)
	td(SPCH-SIMO)M	Delay time, SPICLK high to SPISIMO		10		10
4		valid (clock polarity = 0)					ns
	td(SPCL-SIMO)M	Delay time, SPICLK low to SPISIMO		10		10
		valid (clock polarity = 1)
	tv(SPCL-SIMO)M	Valid time, SPISIMO data valid after	0.5tc(SPC)M – 10		0.5tc(SPC)M + 0.5tc(LCO) – 10
5		SPICLK low (clock polarity = 0)					ns
	tv(SPCH-SIMO)M	Valid time, SPISIMO data valid after	0.5tc(SPC)M – 10		0.5tc(SPC)M + 0.5tc(LCO) – 10
		SPICLK high (clock polarity = 1)
	tsu(SOMI-SPCL)M	Setup time, SPISOMI before SPICLK	35		35
8		low (clock polarity = 0)					ns
	tsu(SOMI-SPCH)M	Setup time, SPISOMI before SPICLK	35		35
		high (clock polarity = 1)
	tv(SPCL-SOMI)M	Valid time, SPISOMI data valid after	0.25tc(SPC)M – 10		0.5tc(SPC)M – 0.5tc(LCO) – 10
9		SPICLK low (clock polarity = 0)					ns
	tv(SPCH-SOMI)M	Valid time, SPISOMI data valid after	0.25tc(SPC)M – 10		0.5tc(SPC)M – 0.5tc(LCO) – 10
		SPICLK high (clock polarity = 1)

(1)The MASTER / SLAVE bit (SPICTL.2) is set and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2)tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR +1)

(3)tc(LCO) = LSPCLK cycle time

(4)Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MAX, slave mode receive 12.5-MHz MAX.

(5)The active edge of the SPICLK signal referenced is controlled by the clock polarity bit (SPICCR.6).

Copyright © 2003–2009, Texas Instruments Incorporated	Electrical Specifications	119
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