Texas Instruments TMS320F2808 Sysclkout DSP Adcenclk Halt Hspclk, ADCINA0, ADCINA7, Epwmsoca SOC

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009 www.ti.com

System

Control Block

High-Speed

Prescaler

SYSCLKOUT

DSP

		ADCENCLK	HALT	HSPCLK
	Analog			Result Registers
	MUX
ADCINA0				Result Reg 0
		S/H		Result Reg 1
ADCINA7
			12-Bit	Result Reg 7
			ADC	Result Reg 8
			Module
ADCINB0
		S/H
ADCINB7				Result Reg 15
			ADC Control Registers
S/W
EPWMSOCA	SOC	Sequencer 1		Sequencer 2	SOC
GPIO/XINT2
_ADCSOC

70A8h

70AFh

70B0h

70B7h

S/W

EPWMSOCB

Figure 4-7. Block Diagram of the ADC Module

To obtain the specified accuracy of the ADC, proper board layout is very critical. To the best extent possible, traces leading to the ADCIN pins should not run in close proximity to the digital signal paths. This is to minimize switching noise on the digital lines from getting coupled to the ADC inputs.

Furthermore, proper isolation techniques must be used to isolate the ADC module power pins (VDD1A18, VDD2A18, VDDA2, VDDAIO) from the digital supply.Figure 4-8shows the ADC pin connections for the 280x devices.

NOTE

1.The ADC registers are accessed at the SYSCLKOUT rate. The internal timing of the ADC module is controlled by the high-speed peripheral clock (HSPCLK).

2.The behavior of the ADC module based on the state of the ADCENCLK and HALT signals is as follows:

–ADCENCLK: On reset, this signal will be low. While reset is active-low (XRS) the clock to the register will still function. This is necessary to make sure all registers and modes go into their default reset state. The analog module, however, will be in a low-power inactive state. As soon as reset goes high, then the clock to the registers will be disabled. When the user sets the ADCENCLK signal high, then the clocks to the registers will be enabled and the analog module will be enabled. There will be a certain time delay (ms range) before the ADC is stable and can be used.

–HALT: This mode only affects the analog module. It does not affect the registers. In this mode, the ADC module goes into low-power mode. This mode also will stop the clock to the CPU, which will stop the HSPCLK; therefore, the ADC register logic will be turned off indirectly.

64 Peripherals Copyright © 2003–2009, Texas Instruments Incorporated

Submit Documentation Feedback

Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

TMS320C2801 TMS320F28016 TMS320F28015