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Texas Instruments TMS320C2801, TMS320F2809 Sampling Window Width for Input Signals, Case, GPIOxn

Models: TMS320F28016 TMS320F2801 TMS320F2802 TMS320F28015 TMS320C2801 TMS320F2806 TMS320F2808 TMS320F2809 TMS320C2802

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009

6.9.3Sampling Window Width for Input Signals

The following section summarizes the sampling window width for input signals for various input qualifier configurations.

Sampling frequency denotes how often a signal is sampled with respect to SYSCLKOUT. Sampling frequency = SYSCLKOUT/(2 * QUALPRD), if QUALPRD ≠ 0

Sampling frequency = SYSCLKOUT, if QUALPRD = 0

Sampling period = SYSCLKOUT cycle x 2 x QUALPRD, if QUALPRD ≠ 0

In the above equations, SYSCLKOUT cycle indicates the time period of SYSCLKOUT.

Sampling period = SYSCLKOUT cycle, if QUALPRD = 0

In a given sampling window, either 3 or 6 samples of the input signal are taken to determine the validity of the signal. This is determined by the value written to GPxQSELn register.

Case 1:

Qualification using 3 samples

Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 2, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 2, if QUALPRD = 0

Case 2:

Qualification using 6 samples

Sampling window width = (SYSCLKOUT cycle x 2 x QUALPRD) x 5, if QUALPRD ≠ 0 Sampling window width = (SYSCLKOUT cycle) x 5, if QUALPRD = 0

XCLKOUT

GPIOxn

tw(GPI)

Figure 6-13. General-Purpose Input Timing

NOTE

The pulse-width requirement for general-purpose input is applicable for the

XINT2_ADCSOC signal as well.

Copyright © 2003–2009, Texas Instruments Incorporated

Electrical Specifications

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Texas Instruments TMS320C2801, TMS320F2809, TMS320F2808, TMS320C2802 Sampling Window Width for Input Signals, Case, GPIOxn

Contents

Data Manual ROM Gpio MUX ROM Timing C280x only Typical Operational Power Versus Frequency F2808 Warm Reset TMS320F2809, TMS320F2808, TMS320F2806 Xclkin Timing Requirements PLL Enabled Check for FeaturesDownload flash programming software Getting StartedAcquire the appropriate development tools Download starter softwareIntroduction Feature TYPE1 Hardware Features 100-MHz DevicesFeature Hardware Features 60-MHz DevicesTMS320F2809, TMS320F2808 100-Pin PZ Lqfp Top View Pin AssignmentsTMS320F2806 100-Pin PZ Lqfp Top View On the C280x devices, the VDD3VFL pin is Vddio TMS320F2801x 100-Pin PZ Lqfp Top View Bottom View Signal Descriptions Signal DescriptionsReset ADC SignalsCPU and I/O Power Pins Gpioa and Peripheral Signals 2 Signal Descriptions TMS320C2801, TMS320F28016, TMS320F28015 TMS320F2809, TMS320F2808, TMS320F2806GPIO33 Protected by the CODE-SECURITY Module Functional Block DiagramF2809 Memory Map Memory MapsF2808 Memory Map F2806 Memory Map F2802, C2802 Memory Map F2801, F28015, F28016, C2801 Memory Map Address Range Program and Data Space Addresses of Flash Sectors in F2809Addresses of Flash Sectors in F2808 Addresses of Flash Sectors in F2806, F2802Impact of Using the Code Security Module Addresses of Flash Sectors in F2801, F28015, F28016Address Flash ROM H0 Saram Wait-statesArea WAIT-STATES Comments OTPPeripheral Bus Brief Descriptions1 C28x CPU Memory Bus Harvard Bus Architecture7 M0, M1 SARAMs Real-Time Jtag and AnalysisFlash 6 ROMBoot ROM Boot Mode Selection8 L0, L1, H0 SARAMs Disclaimer Code Security Module Disclaimer SecurityOscillator and PLL Low-Power ModesPeripheral Interrupt Expansion PIE Block External Interrupts XINT1, XINT2, XnmiControl Peripherals 19 32-Bit CPU-Timers 0, 1Peripheral Frames 0, 1, 2 PFn General-Purpose Input/Output Gpio MultiplexerRegister Map Serial Port PeripheralsName Address Range Access TypePeripheral Frame 0 Registers1 Peripheral Frame 1 Registers111. Device Emulation Registers Device Emulation RegistersInterrupts 10. Peripheral Frame 2 Registers1External and PIE Interrupt Sources INT1 INT2 INT11 INT12 MUXIntm 13. PIE Configuration and Control Registers External Interrupts14. External Interrupt Registers System Control OSC and PLL Block 15. PLL, Clocking, Watchdog, and Low-Power Mode Registers1Crystal External Clock Signal Toggling 0 −V DD16. Pllcr Register Bit Definitions 17. Possible PLL Configuration ModesPLL Mode Remarks Pllstsclkindiv Sysclkout Clkin PLL-Based Clock ModuleLoss of Input Clock Watchdog Block Oscclk Clkin Sysclkout Low-Power Modes Block18. Low-Power Modes LPMCR010Pschpsc TCR.4 32-Bit CPU-Timers 0/1/2Tddrhtddr PrdhprdCPU-Timers 0, 1, 2 Configuration and Control Registers Enhanced PWM Modules ePWM1/2/3/4/5/6 EPWM Control and Status Registers EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 Size#SHADOW CTR = Zero Enhanced CAP Modules eCAP1/2/3/4 Hi-Resolution PWM HrpwmCTR=PRD CTR=CMP CtrphsCtrovf OVF RSTECAP Control and Status Registers ECAP1 ECAP2 ECAP3 ECAP4Size Description Enhanced QEP Modules eQEP1/2 Address #SHADOW EQEP Control and Status RegistersEQEP1 EQEP2 Register DescriptionEnhanced Analog-to-Digital Converter ADC Module ADCINB0 ADCINB7 Sysclkout DSP Adcenclk Halt HspclkADCINA0 ADCINA7Adcrefin ADCINA70ADCINB70 AdcloAdcresext ADC Connections if the ADC Is Not UsedADC Registers1 ADC RegistersPeripherals Can Bus TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802 SN65HVD23x11. eCAN-A Memory Map 12. eCAN-B Memory Map Size Description Address Can Register Map1Register Name ECAN-A ECAN-BSerial Communications Interface SCI Modules SCI-A, SCI-B SCI-B Registers1 SCI-A Registers113. Serial Communications Interface SCI Module Block Diagram When Spibrr = 3 to 11. SPI-B Registers 10. SPI-A Registers13. SPI-D Registers 12. SPI-C Registers−−−−− 14. SPI Module Block Diagram Slave ModeInter-Integrated Circuit I2C Sysrs 14. I2C-A RegistersGpio MUX Sdaa Scla I2CAENCLK I2C−A C28X CPU SysclkoutGpioxnmisel Gpiolmpsel GPIOXINT1SEL GPIOXINT2SEL15. Gpio Registers Gpio Control Registers Eallow ProtectedGpio Data Registers not Eallow Protected GPAMUX2 16. F2808 Gpio MUX TableGPAMUX1/2 GPAMUX1Sync Sysclkout Time between samples GPyCTRL Reg GPIOxDevice and Development Support Tool Nomenclature Software Development ToolsHardware Development Tools Device Family Temperature RangeTMS PrefixPeripheral Guide Documentation SupportTMS320x280x, 2801x Peripheral Selection Guide LiteratureApplication Programming Interface API Reference TMS320C28xC28x FPU Primer Application Reports and SoftwareTMS320x281x to TMS320x2833x or 2823x Migration Overview TMS320x280x to TMS320x2833x or 2823x Migration OverviewSoftware SPRA820Device Support Absolute Maximum Ratings1 Electrical SpecificationsParameter Test Conditions MIN TYP MAX Unit Electrical CharacteristicsRecommended Operating Conditions MIN NOM MAX UnitSysclkout Current ConsumptionTYP5 MAX6 SCI-A SPI-A ADC TYP4 MAX5 SCI SPI Reducing Current ConsumptionPeripheral DD Current Module ADC I2CIddio Total PowerCurrent Consumption Graphs IDD IDDA18Typical Operational Current Versus Frequency C280x Typical Operational Power Versus Frequency C280xEMU0 EMU1 Trst TMS TDI TDO TCK DSP GND Tckret Jtagheader Emulator Connection Without Signal Buffering for the DSP85 pF Timing Parameter SymbologyGeneral Notes on Timing Parameters Test Load CircuitTMS320x280x Clock Table and Nomenclature 100-MHz Devices Device Clock TableInput Clock Frequency Clock Requirements and CharacteristicsXCLKIN1 Timing Requirements PLL Enabled 10. XCLKIN1 Timing Requirements PLL DisabledXclkina Xclkoutb Power SequencingPower Management and Supervisory Circuit Solutions 12. Power Management and Supervisory Circuit SolutionsOSCCLK/8A Xclkout13. Reset XRS Timing Requirements Xclkout XRSOSCCLK/8 Sysclkout Oscclk OSCCLK/2 14. General-Purpose Output Switching CharacteristicsGeneral-Purpose Input/Output Gpio Gpio Output TimingOutput From Qualifier Gpio Signal GPxQSELn = 1,0 6 samplesGpio Input Timing Sysclkout Qualprd = 1 SYSCLKOUT/2Sampling Window Width for Input Signals CaseGPIOxn Address/Data Internal Low-Power Mode Wakeup Timing16. Idle Mode Timing Requirements1 17. Idle Mode Switching Characteristics1Xclkin Xclkout Standby 18. Standby Mode Timing Requirements19. Standby Mode Switching Characteristics Test Conditions MIN NOM MAX Unit21. Halt Mode Switching Characteristics 20. Halt Mode Timing RequirementsTrip-Zone Input Timing 23. ePWM Switching CharacteristicsEnhanced Control Peripherals Enhanced Pulse Width Modulator ePWM TimingMIN TYP MAX Unit 27. eCAP Switching Characteristics29. eQEP Switching Characteristics 26. Enhanced Capture eCAP Timing Requirement1Adcsocbo 32. External Interrupt Switching Characteristics1External Interrupt Timing ParameterVddio 10.4 I2C Electrical Specification and TimingSerial Peripheral Interface SPI Master Mode Timing 33. I2C Timing34. SPI Master Mode External Timing Clock Phase = 0 1 2 3 4 Spisimo Spisomi Master In Data Must Be ValidSpistea 35. SPI Master Mode External Timing Clock Phase = 1 1 2 3 4 Spisomi SpiclkClock polarity = Data Valid36. SPI Slave Mode External Timing Clock Phase = 01 2 3 4 SPI Slave Mode TimingSpisimo Data Must Be Valid 37. SPI Slave Mode External Timing Clock Phase = 11 2On-Chip Analog-to-Digital Converter ADC Power-Up Control Bit Timing ADCIN0 Analog InputsConverter Conversion ModesSequential Sampling Mode Single-Channel Smode = AT 12.5 MHz Sample n Sample n +ADC Clock Remarks Simultaneous Sampling Mode Dual-Channel Smode = Detailed Descriptions Flash Timing 43. Flash Endurance for a and S Temperature Material144. Flash Endurance for Q Temperature Material1 46. Flash/OTP Access TimingFlash Flash Random OTP WAIT-STATE 48. ROM/OTP Access TimingROM Timing C280x only Sysclkout nsMigration Issues ADDITIONS, DELETIONS, and Modifications C280x Thermal Model 100-pin PZ Results F280x Thermal Model 100-pin GGM ResultsF280x Thermal Model 100-pin PZ Results C280x Thermal Model 100-pin GGM ResultsΨJTC/W F2809 Thermal Model 100-pin PZ ResultsPackage Type Pins Package Qty Eco Plan Lead Orderable DeviceSamples Package Qty Eco Plan Lead Microstar TMS320F2806GGMS Active TMS320F2802ZGMA ActiveTMS320F2802ZGMS Active TMS320F2806GGMA ActiveTMS320F2809ZGMS Active TMS320F2809ZGMA Active4145257-3/C 12/01 GGM S-PBGA-N10010,10 20 TYP 40 MAXPage Plastic Quad Flatpack PZ S-PQFP-G100Products Applications DSPRfid