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Texas Instruments TMS320F2806 GGM S-PBGA-N100, 10,10 20 TYP, 40 MAX, 4145257-3/C 12/01

Models: TMS320F28016 TMS320F2801 TMS320F2802 TMS320F28015 TMS320C2801 TMS320F2806 TMS320F2808 TMS320F2809 TMS320C2802

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MECHANICAL DATA

					MPBG028B FEBRUARY 1997 – REVISED MAY 2002
GGM (S–PBGA–N100)								PLASTIC BALL GRID ARRAY
10,10	SQ						7,20 TYP
9,90	SQ				0,80		7,20 TYP
					0,80
										0,40
			K
			J
			H									0,80
			G									0,80
			G
			F
			E
			D									0,40
			C									0,40
			B
			A
		A1 Corner	1	2	3	4	5	6	7	8	9	10
			1	2	3	4	5	6	7	8	9	10
0,95							Bottom View
0,95
0,85		1,40 MAX
			Seating Plane
0,55	0,08	0,45	0,10
0,45	0,08	0,45	0,10
0,45		0,35
		0,35
												4145257–3/C 12/01

NOTES: A. All linear dimensions are in millimeters.

B.This drawing is subject to change without notice

C.MicroStar BGA configuration.

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

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Image 141

Texas Instruments TMS320F2806, TMS320F2809, TMS320F2808 GGM S-PBGA-N100, 10,10 20 TYP, 40 MAX, 4145257-3/C 12/01

Contents

Data Manual ROM Gpio MUX ROM Timing C280x only Typical Operational Power Versus Frequency F2808 Warm Reset TMS320F2809, TMS320F2808, TMS320F2806 Xclkin Timing Requirements PLL Enabled Check for FeaturesAcquire the appropriate development tools Getting StartedDownload starter software Download flash programming softwareIntroduction Feature TYPE1 Hardware Features 100-MHz DevicesFeature Hardware Features 60-MHz DevicesTMS320F2809, TMS320F2808 100-Pin PZ Lqfp Top View Pin AssignmentsTMS320F2806 100-Pin PZ Lqfp Top View On the C280x devices, the VDD3VFL pin is Vddio TMS320F2801x 100-Pin PZ Lqfp Top View Bottom View Signal Descriptions Signal DescriptionsReset ADC SignalsCPU and I/O Power Pins Gpioa and Peripheral Signals 2 Signal Descriptions TMS320C2801, TMS320F28016, TMS320F28015 TMS320F2809, TMS320F2808, TMS320F2806GPIO33 Protected by the CODE-SECURITY Module Functional Block DiagramF2809 Memory Map Memory MapsF2808 Memory Map F2806 Memory Map F2802, C2802 Memory Map F2801, F28015, F28016, C2801 Memory Map Addresses of Flash Sectors in F2808 Addresses of Flash Sectors in F2809Addresses of Flash Sectors in F2806, F2802 Address Range Program and Data SpaceImpact of Using the Code Security Module Addresses of Flash Sectors in F2801, F28015, F28016Address Flash ROM Area WAIT-STATES Comments Wait-statesOTP H0 Saram1 C28x CPU Brief DescriptionsMemory Bus Harvard Bus Architecture Peripheral BusFlash Real-Time Jtag and Analysis6 ROM 7 M0, M1 SARAMsBoot ROM Boot Mode Selection8 L0, L1, H0 SARAMs Disclaimer Code Security Module Disclaimer SecurityPeripheral Interrupt Expansion PIE Block Low-Power ModesExternal Interrupts XINT1, XINT2, Xnmi Oscillator and PLLPeripheral Frames 0, 1, 2 PFn 19 32-Bit CPU-Timers 0, 1General-Purpose Input/Output Gpio Multiplexer Control PeripheralsRegister Map Serial Port PeripheralsPeripheral Frame 0 Registers1 Access TypePeripheral Frame 1 Registers1 Name Address RangeInterrupts Device Emulation Registers10. Peripheral Frame 2 Registers1 11. Device Emulation RegistersExternal and PIE Interrupt Sources INT1 INT2 INT11 INT12 MUXIntm 13. PIE Configuration and Control Registers External Interrupts14. External Interrupt Registers System Control OSC and PLL Block 15. PLL, Clocking, Watchdog, and Low-Power Mode Registers1Crystal External Clock Signal Toggling 0 −V DDPLL Mode Remarks Pllstsclkindiv Sysclkout Clkin 17. Possible PLL Configuration ModesPLL-Based Clock Module 16. Pllcr Register Bit DefinitionsLoss of Input Clock Watchdog Block 18. Low-Power Modes Low-Power Modes BlockLPMCR010 Oscclk Clkin SysclkoutTddrhtddr 32-Bit CPU-Timers 0/1/2Prdhprd Pschpsc TCR.4CPU-Timers 0, 1, 2 Configuration and Control Registers Enhanced PWM Modules ePWM1/2/3/4/5/6 EPWM Control and Status Registers EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 Size#SHADOW CTR = Zero Enhanced CAP Modules eCAP1/2/3/4 Hi-Resolution PWM HrpwmCtrovf OVF CtrphsRST CTR=PRD CTR=CMPECAP Control and Status Registers ECAP1 ECAP2 ECAP3 ECAP4Size Description Enhanced QEP Modules eQEP1/2 EQEP1 EQEP2 EQEP Control and Status RegistersRegister Description Address #SHADOWEnhanced Analog-to-Digital Converter ADC Module ADCINA0 Sysclkout DSP Adcenclk Halt HspclkADCINA7 ADCINB0 ADCINB7ADCINB70 ADCINA70Adclo AdcrefinAdcresext ADC Connections if the ADC Is Not UsedADC Registers1 ADC RegistersPeripherals TMS320F2802, TMS320F2801, TMS320C2802 TMS320F2809, TMS320F2808, TMS320F2806SN65HVD23x Can Bus11. eCAN-A Memory Map 12. eCAN-B Memory Map Register Name Can Register Map1ECAN-A ECAN-B Size Description AddressSerial Communications Interface SCI Modules SCI-A, SCI-B SCI-B Registers1 SCI-A Registers113. Serial Communications Interface SCI Module Block Diagram When Spibrr = 3 to 11. SPI-B Registers 10. SPI-A Registers13. SPI-D Registers 12. SPI-C Registers−−−−− 14. SPI Module Block Diagram Slave ModeInter-Integrated Circuit I2C Gpio MUX Sdaa Scla 14. I2C-A RegistersI2CAENCLK I2C−A C28X CPU Sysclkout SysrsGpioxnmisel Gpiolmpsel GPIOXINT1SEL GPIOXINT2SEL15. Gpio Registers Gpio Control Registers Eallow ProtectedGpio Data Registers not Eallow Protected GPAMUX1/2 16. F2808 Gpio MUX TableGPAMUX1 GPAMUX2Sync Sysclkout Time between samples GPyCTRL Reg GPIOxDevice and Development Support Tool Nomenclature Software Development ToolsHardware Development Tools TMS Temperature RangePrefix Device FamilyTMS320x280x, 2801x Peripheral Selection Guide Documentation SupportLiterature Peripheral GuideApplication Programming Interface API Reference TMS320C28xTMS320x281x to TMS320x2833x or 2823x Migration Overview Application Reports and SoftwareTMS320x280x to TMS320x2833x or 2823x Migration Overview C28x FPU PrimerSoftware SPRA820Device Support Absolute Maximum Ratings1 Electrical SpecificationsRecommended Operating Conditions Electrical CharacteristicsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX UnitSysclkout Current ConsumptionTYP5 MAX6 SCI-A SPI-A ADC TYP4 MAX5 Peripheral DD Current Module Reducing Current ConsumptionADC I2C SCI SPICurrent Consumption Graphs Total PowerIDD IDDA18 IddioTypical Operational Current Versus Frequency C280x Typical Operational Power Versus Frequency C280xEMU0 EMU1 Trst TMS TDI TDO TCK DSP GND Tckret Jtagheader Emulator Connection Without Signal Buffering for the DSPGeneral Notes on Timing Parameters Timing Parameter SymbologyTest Load Circuit 85 pFTMS320x280x Clock Table and Nomenclature 100-MHz Devices Device Clock TableXCLKIN1 Timing Requirements PLL Enabled Clock Requirements and Characteristics10. XCLKIN1 Timing Requirements PLL Disabled Input Clock FrequencyPower Management and Supervisory Circuit Solutions Power Sequencing12. Power Management and Supervisory Circuit Solutions Xclkina XclkoutbOSCCLK/8A Xclkout13. Reset XRS Timing Requirements Xclkout XRSOSCCLK/8 General-Purpose Input/Output Gpio 14. General-Purpose Output Switching CharacteristicsGpio Output Timing Sysclkout Oscclk OSCCLK/2Gpio Input Timing Gpio Signal GPxQSELn = 1,0 6 samplesSysclkout Qualprd = 1 SYSCLKOUT/2 Output From QualifierSampling Window Width for Input Signals CaseGPIOxn 16. Idle Mode Timing Requirements1 Low-Power Mode Wakeup Timing17. Idle Mode Switching Characteristics1 Address/Data Internal19. Standby Mode Switching Characteristics 18. Standby Mode Timing RequirementsTest Conditions MIN NOM MAX Unit Xclkin Xclkout Standby21. Halt Mode Switching Characteristics 20. Halt Mode Timing RequirementsEnhanced Control Peripherals 23. ePWM Switching CharacteristicsEnhanced Pulse Width Modulator ePWM Timing Trip-Zone Input Timing29. eQEP Switching Characteristics 27. eCAP Switching Characteristics26. Enhanced Capture eCAP Timing Requirement1 MIN TYP MAX UnitExternal Interrupt Timing 32. External Interrupt Switching Characteristics1Parameter AdcsocboSerial Peripheral Interface SPI Master Mode Timing 10.4 I2C Electrical Specification and Timing33. I2C Timing Vddio34. SPI Master Mode External Timing Clock Phase = 0 1 2 3 4 Spisimo Spisomi Master In Data Must Be ValidSpistea 35. SPI Master Mode External Timing Clock Phase = 1 1 2 3 4 Clock polarity = SpiclkData Valid Spisomi36. SPI Slave Mode External Timing Clock Phase = 01 2 3 4 SPI Slave Mode TimingSpisimo Data Must Be Valid 37. SPI Slave Mode External Timing Clock Phase = 11 2On-Chip Analog-to-Digital Converter ADC Power-Up Control Bit Timing Converter Analog InputsConversion Modes ADCIN0Sequential Sampling Mode Single-Channel Smode = AT 12.5 MHz Sample n Sample n +ADC Clock Remarks Simultaneous Sampling Mode Dual-Channel Smode = Detailed Descriptions 44. Flash Endurance for Q Temperature Material1 43. Flash Endurance for a and S Temperature Material146. Flash/OTP Access Timing Flash TimingROM Timing C280x only 48. ROM/OTP Access TimingSysclkout ns Flash Flash Random OTP WAIT-STATEMigration Issues ADDITIONS, DELETIONS, and Modifications F280x Thermal Model 100-pin PZ Results F280x Thermal Model 100-pin GGM ResultsC280x Thermal Model 100-pin GGM Results C280x Thermal Model 100-pin PZ ResultsΨJTC/W F2809 Thermal Model 100-pin PZ ResultsPackage Type Pins Package Qty Eco Plan Lead Orderable DeviceSamples Package Qty Eco Plan Lead TMS320F2802ZGMS Active TMS320F2802ZGMA ActiveTMS320F2806GGMA Active Microstar TMS320F2806GGMS ActiveTMS320F2809ZGMS Active TMS320F2809ZGMA Active10,10 20 TYP GGM S-PBGA-N10040 MAX 4145257-3/C 12/01Page Plastic Quad Flatpack PZ S-PQFP-G100Products Applications DSPRfid