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Texas Instruments TMS320F2806, TMS320F2809, TMS320F2808, TMS320C2802, TMS320C2801 Watchdog Block

Models: TMS320F28016 TMS320F2801 TMS320F2802 TMS320F28015 TMS320C2801 TMS320F2806 TMS320F2808 TMS320F2809 TMS320C2802

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

www.ti.com

SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009

3.6.2Watchdog Block

The watchdog block on the 280x is similar to the one used on the 240x and 281x devices. The watchdog module generates an output pulse, 512 oscillator clocks wide (OSCCLK), whenever the 8-bit watchdog up counter has reached its maximum value. To prevent this, the user disables the counter or the software must periodically write a 0x55 + 0xAA sequence into the watchdog key register which will reset the watchdog counter. Figure 3-14shows the various functional blocks within the watchdog module.

WDCR (WDPS(2:0))

WDCR (WDDIS)

					WDCNTR(7:0)
OSCCLK	/512	Watchdog	WDCLK		8-Bit
	/512	Prescaler			Watchdog
		Prescaler			Watchdog
					Counter
					CLR
				Clear Counter
Internal
Pullup
	WDKEY(7:0)				Generate	WDRST
						WDRST
	Watchdog
	Watchdog				Output Pulse	WDINT
	55 + AA				Output Pulse	WDINT
	55 + AA	Good Key			(512 OSCCLKs)
	Key Detector	Good Key			(512 OSCCLKs)
	Key Detector
XRS
		Core-reset		Bad	SCSR (WDENINT)
		Core-reset		WDCHK


		WDCR (WDCHK(2:0))		Key
		WDCR (WDCHK(2:0))

WDRST(A)

1

0

1

A.The WDRST signal is driven low for 512 OSCCLK cycles.

Figure 3-14. Watchdog Module

The WDINT signal enables the watchdog to be used as a wakeup from IDLE/STANDBY mode.

In STANDBY mode, all peripherals are turned off on the device. The only peripheral that remains functional is the watchdog. The WATCHDOG module will run off OSCCLK. The WDINT signal is fed to the LPM block so that it can wake the device from STANDBY (if enabled). See Section 3.7, Low-Power Modes Block, for more details.

In IDLE mode, the WDINT signal can generate an interrupt to the CPU, via the PIE, to take the CPU out of IDLE mode.

In HALT mode, this feature cannot be used because the oscillator (and PLL) are turned off and hence so is the WATCHDOG.

Copyright © 2003–2009, Texas Instruments Incorporated

Functional Overview

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TMS320C2801 TMS320F28016 TMS320F28015

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Texas Instruments TMS320F2806, TMS320F2809, TMS320F2808, TMS320C2802, TMS320C2801, TMS320F28016, TMS320F28015 Watchdog Block

Contents

Data Manual ROM Gpio MUX ROM Timing C280x only Typical Operational Power Versus Frequency F2808 Warm Reset TMS320F2809, TMS320F2808, TMS320F2806 Xclkin Timing Requirements PLL Enabled Check for Features Download flash programming software Getting StartedAcquire the appropriate development tools Download starter software Introduction Feature TYPE1 Hardware Features 100-MHz Devices Feature Hardware Features 60-MHz Devices TMS320F2809, TMS320F2808 100-Pin PZ Lqfp Top View Pin Assignments TMS320F2806 100-Pin PZ Lqfp Top View On the C280x devices, the VDD3VFL pin is Vddio TMS320F2801x 100-Pin PZ Lqfp Top View Bottom View Signal Descriptions Signal Descriptions Reset ADC SignalsCPU and I/O Power Pins Gpioa and Peripheral Signals 2 Signal Descriptions TMS320C2801, TMS320F28016, TMS320F28015 TMS320F2809, TMS320F2808, TMS320F2806 GPIO33 Protected by the CODE-SECURITY Module Functional Block Diagram F2809 Memory Map Memory Maps F2808 Memory Map F2806 Memory Map F2802, C2802 Memory Map F2801, F28015, F28016, C2801 Memory Map Address Range Program and Data Space Addresses of Flash Sectors in F2809Addresses of Flash Sectors in F2808 Addresses of Flash Sectors in F2806, F2802 Impact of Using the Code Security Module Addresses of Flash Sectors in F2801, F28015, F28016Address Flash ROM H0 Saram Wait-statesArea WAIT-STATES Comments OTP Peripheral Bus Brief Descriptions1 C28x CPU Memory Bus Harvard Bus Architecture 7 M0, M1 SARAMs Real-Time Jtag and AnalysisFlash 6 ROM Boot ROM Boot Mode Selection8 L0, L1, H0 SARAMs Disclaimer Code Security Module Disclaimer Security Oscillator and PLL Low-Power ModesPeripheral Interrupt Expansion PIE Block External Interrupts XINT1, XINT2, Xnmi Control Peripherals 19 32-Bit CPU-Timers 0, 1Peripheral Frames 0, 1, 2 PFn General-Purpose Input/Output Gpio Multiplexer Register Map Serial Port Peripherals Name Address Range Access TypePeripheral Frame 0 Registers1 Peripheral Frame 1 Registers1 11. Device Emulation Registers Device Emulation RegistersInterrupts 10. Peripheral Frame 2 Registers1 External and PIE Interrupt Sources INT1 INT2 INT11 INT12 MUXIntm 13. PIE Configuration and Control Registers External Interrupts14. External Interrupt Registers System Control OSC and PLL Block 15. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 Crystal External Clock Signal Toggling 0 −V DD 16. Pllcr Register Bit Definitions 17. Possible PLL Configuration ModesPLL Mode Remarks Pllstsclkindiv Sysclkout Clkin PLL-Based Clock Module Loss of Input Clock Watchdog Block Oscclk Clkin Sysclkout Low-Power Modes Block18. Low-Power Modes LPMCR010 Pschpsc TCR.4 32-Bit CPU-Timers 0/1/2Tddrhtddr Prdhprd CPU-Timers 0, 1, 2 Configuration and Control Registers Enhanced PWM Modules ePWM1/2/3/4/5/6 EPWM Control and Status Registers EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 Size#SHADOW CTR = Zero Enhanced CAP Modules eCAP1/2/3/4 Hi-Resolution PWM Hrpwm CTR=PRD CTR=CMP CtrphsCtrovf OVF RST ECAP Control and Status Registers ECAP1 ECAP2 ECAP3 ECAP4Size Description Enhanced QEP Modules eQEP1/2 Address #SHADOW EQEP Control and Status RegistersEQEP1 EQEP2 Register Description Enhanced Analog-to-Digital Converter ADC Module ADCINB0 ADCINB7 Sysclkout DSP Adcenclk Halt HspclkADCINA0 ADCINA7 Adcrefin ADCINA70ADCINB70 Adclo Adcresext ADC Connections if the ADC Is Not Used ADC Registers1 ADC Registers Peripherals Can Bus TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802 SN65HVD23x 11. eCAN-A Memory Map 12. eCAN-B Memory Map Size Description Address Can Register Map1Register Name ECAN-A ECAN-B Serial Communications Interface SCI Modules SCI-A, SCI-B SCI-B Registers1 SCI-A Registers1 13. Serial Communications Interface SCI Module Block Diagram When Spibrr = 3 to 11. SPI-B Registers 10. SPI-A Registers 13. SPI-D Registers 12. SPI-C Registers −−−−− 14. SPI Module Block Diagram Slave Mode Inter-Integrated Circuit I2C Sysrs 14. I2C-A RegistersGpio MUX Sdaa Scla I2CAENCLK I2C−A C28X CPU Sysclkout Gpioxnmisel Gpiolmpsel GPIOXINT1SEL GPIOXINT2SEL 15. Gpio Registers Gpio Control Registers Eallow ProtectedGpio Data Registers not Eallow Protected GPAMUX2 16. F2808 Gpio MUX TableGPAMUX1/2 GPAMUX1 Sync Sysclkout Time between samples GPyCTRL Reg GPIOx Device and Development Support Tool Nomenclature Software Development ToolsHardware Development Tools Device Family Temperature RangeTMS Prefix Peripheral Guide Documentation SupportTMS320x280x, 2801x Peripheral Selection Guide Literature Application Programming Interface API Reference TMS320C28x C28x FPU Primer Application Reports and SoftwareTMS320x281x to TMS320x2833x or 2823x Migration Overview TMS320x280x to TMS320x2833x or 2823x Migration Overview Software SPRA820 Device Support Absolute Maximum Ratings1 Electrical Specifications Parameter Test Conditions MIN TYP MAX Unit Electrical CharacteristicsRecommended Operating Conditions MIN NOM MAX Unit Sysclkout Current Consumption TYP5 MAX6 SCI-A SPI-A ADC TYP4 MAX5 SCI SPI Reducing Current ConsumptionPeripheral DD Current Module ADC I2C Iddio Total PowerCurrent Consumption Graphs IDD IDDA18 Typical Operational Current Versus Frequency C280x Typical Operational Power Versus Frequency C280x EMU0 EMU1 Trst TMS TDI TDO TCK DSP GND Tckret Jtagheader Emulator Connection Without Signal Buffering for the DSP 85 pF Timing Parameter SymbologyGeneral Notes on Timing Parameters Test Load Circuit TMS320x280x Clock Table and Nomenclature 100-MHz Devices Device Clock Table Input Clock Frequency Clock Requirements and CharacteristicsXCLKIN1 Timing Requirements PLL Enabled 10. XCLKIN1 Timing Requirements PLL Disabled Xclkina Xclkoutb Power SequencingPower Management and Supervisory Circuit Solutions 12. Power Management and Supervisory Circuit Solutions OSCCLK/8A Xclkout 13. Reset XRS Timing Requirements Xclkout XRSOSCCLK/8 Sysclkout Oscclk OSCCLK/2 14. General-Purpose Output Switching CharacteristicsGeneral-Purpose Input/Output Gpio Gpio Output Timing Output From Qualifier Gpio Signal GPxQSELn = 1,0 6 samplesGpio Input Timing Sysclkout Qualprd = 1 SYSCLKOUT/2 Sampling Window Width for Input Signals CaseGPIOxn Address/Data Internal Low-Power Mode Wakeup Timing16. Idle Mode Timing Requirements1 17. Idle Mode Switching Characteristics1 Xclkin Xclkout Standby 18. Standby Mode Timing Requirements19. Standby Mode Switching Characteristics Test Conditions MIN NOM MAX Unit 21. Halt Mode Switching Characteristics 20. Halt Mode Timing Requirements Trip-Zone Input Timing 23. ePWM Switching CharacteristicsEnhanced Control Peripherals Enhanced Pulse Width Modulator ePWM Timing MIN TYP MAX Unit 27. eCAP Switching Characteristics29. eQEP Switching Characteristics 26. Enhanced Capture eCAP Timing Requirement1 Adcsocbo 32. External Interrupt Switching Characteristics1External Interrupt Timing Parameter Vddio 10.4 I2C Electrical Specification and TimingSerial Peripheral Interface SPI Master Mode Timing 33. I2C Timing 34. SPI Master Mode External Timing Clock Phase = 0 1 2 3 4 Spisimo Spisomi Master In Data Must Be ValidSpistea 35. SPI Master Mode External Timing Clock Phase = 1 1 2 3 4 Spisomi SpiclkClock polarity = Data Valid 36. SPI Slave Mode External Timing Clock Phase = 01 2 3 4 SPI Slave Mode Timing Spisimo Data Must Be Valid 37. SPI Slave Mode External Timing Clock Phase = 11 2 On-Chip Analog-to-Digital Converter ADC Power-Up Control Bit Timing ADCIN0 Analog InputsConverter Conversion Modes Sequential Sampling Mode Single-Channel Smode = AT 12.5 MHz Sample n Sample n +ADC Clock Remarks Simultaneous Sampling Mode Dual-Channel Smode = Detailed Descriptions Flash Timing 43. Flash Endurance for a and S Temperature Material144. Flash Endurance for Q Temperature Material1 46. Flash/OTP Access Timing Flash Flash Random OTP WAIT-STATE 48. ROM/OTP Access TimingROM Timing C280x only Sysclkout ns Migration Issues ADDITIONS, DELETIONS, and Modifications C280x Thermal Model 100-pin PZ Results F280x Thermal Model 100-pin GGM ResultsF280x Thermal Model 100-pin PZ Results C280x Thermal Model 100-pin GGM Results ΨJTC/W F2809 Thermal Model 100-pin PZ Results Package Type Pins Package Qty Eco Plan Lead Orderable DeviceSamples Package Qty Eco Plan Lead Microstar TMS320F2806GGMS Active TMS320F2802ZGMA ActiveTMS320F2802ZGMS Active TMS320F2806GGMA Active TMS320F2809ZGMS Active TMS320F2809ZGMA Active 4145257-3/C 12/01 GGM S-PBGA-N10010,10 20 TYP 40 MAXPage Plastic Quad Flatpack PZ S-PQFP-G100 Products Applications DSPRfid