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Texas Instruments TMS320F2806 Clock Requirements and Characteristics, Input Clock Frequency

Models: TMS320F28016 TMS320F2801 TMS320F2802 TMS320F28015 TMS320C2801 TMS320F2806 TMS320F2808 TMS320F2809 TMS320C2802

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

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SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009

6.7Clock Requirements and Characteristics

Table 6-8. Input Clock Frequency

		PARAMETER			MIN TYP	MAX	UNIT

			Resonator (X1/X2)		20	35

	fx	Input clock frequency	Crystal (X1/X2)		20	35	MHz

			External oscillator/clock	100-MHz device	4	100
			External oscillator/clock	100-MHz device	4	100
			source (XCLKIN or X1 pin)	60-MHz device	4	60

	fl	Limp mode SYSCLKOUT frequency range (with /2 enabled)			1–5		MHz

Table 6-9. XCLKIN(1) Timing Requirements - PLL Enabled

NO.			MIN	MAX	UNIT

C8	tc(CI)	Cycle time, XCLKIN	33.3	200	ns
C9	tf(CI)	Fall time, XCLKIN		6	ns
C10	tr(CI)	Rise time, XCLKIN		6	ns
C11	tw(CIL)	Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)	45	55	%
C12	tw(CIH)	Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)	45	55	%

(1)This applies to the X1 pin also.

Table 6-10. XCLKIN(1) Timing Requirements - PLL Disabled

NO.				MIN	MAX	UNIT

C8	tc(CI)	Cycle time, XCLKIN	100-MHz device	10	250	ns
			60-MHz device	16.67	250

C9	tf(CI)	Fall time, XCLKIN	Up to 20 MHz		6	ns
			20 MHz to 100 MHz		2	ns

C10	tr(CI)	Rise time, XCLKIN	Up to 20 MHz		6	ns
			20 MHz to 100 MHz		2	ns

C11	tw(CIL)	Pulse duration, XCLKIN low as a percentage of tc(OSCCLK)		45	55	%
C12	tw(CIH)	Pulse duration, XCLKIN high as a percentage of tc(OSCCLK)		45	55	%

(1)This applies to the X1 pin also.

The possible configuration modes are shown in Table 3-17.

Table 6-11. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)(1) (2)

NO.		PARAMETER		MIN TYP		MAX	UNIT

C1	tc(XCO)	Cycle time, XCLKOUT	100-MHz device	10			ns

			60-MHz device	16.67
			60-MHz device	16.67

C3	tf(XCO)	Fall time, XCLKOUT		2			ns
C4	tr(XCO)	Rise time, XCLKOUT		2			ns
C5	tw(XCOL)	Pulse duration, XCLKOUT low		H – 2		H + 2	ns
C6	tw(XCOH)	Pulse duration, XCLKOUT high		H – 2		H + 2	ns
	tp	PLL lock time				(3)	cycles
	tp	PLL lock time				131072tc(OSCCLK)	cycles

(1)A load of 40 pF is assumed for these parameters.

(2)H = 0.5tc(XCO)

(3)OSCCLK is either the output of the on-chip oscillator or the output from an external oscillator.

Copyright © 2003–2009, Texas Instruments Incorporated

Electrical Specifications

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Texas Instruments TMS320F2806, TMS320F2809, TMS320F2808 Clock Requirements and Characteristics, Input Clock Frequency

Contents

Data Manual ROM Gpio MUX ROM Timing C280x only Typical Operational Power Versus Frequency F2808 Warm Reset TMS320F2809, TMS320F2808, TMS320F2806 Xclkin Timing Requirements PLL Enabled Check for Features Acquire the appropriate development tools Getting StartedDownload starter software Download flash programming software Introduction Feature TYPE1 Hardware Features 100-MHz Devices Feature Hardware Features 60-MHz Devices TMS320F2809, TMS320F2808 100-Pin PZ Lqfp Top View Pin Assignments TMS320F2806 100-Pin PZ Lqfp Top View On the C280x devices, the VDD3VFL pin is Vddio TMS320F2801x 100-Pin PZ Lqfp Top View Bottom View Signal Descriptions Signal Descriptions Reset ADC SignalsCPU and I/O Power Pins Gpioa and Peripheral Signals 2 Signal Descriptions TMS320C2801, TMS320F28016, TMS320F28015 TMS320F2809, TMS320F2808, TMS320F2806 GPIO33 Protected by the CODE-SECURITY Module Functional Block Diagram F2809 Memory Map Memory Maps F2808 Memory Map F2806 Memory Map F2802, C2802 Memory Map F2801, F28015, F28016, C2801 Memory Map Addresses of Flash Sectors in F2808 Addresses of Flash Sectors in F2809Addresses of Flash Sectors in F2806, F2802 Address Range Program and Data Space Impact of Using the Code Security Module Addresses of Flash Sectors in F2801, F28015, F28016Address Flash ROM Area WAIT-STATES Comments Wait-statesOTP H0 Saram 1 C28x CPU Brief DescriptionsMemory Bus Harvard Bus Architecture Peripheral Bus Flash Real-Time Jtag and Analysis6 ROM 7 M0, M1 SARAMs Boot ROM Boot Mode Selection8 L0, L1, H0 SARAMs Disclaimer Code Security Module Disclaimer Security Peripheral Interrupt Expansion PIE Block Low-Power ModesExternal Interrupts XINT1, XINT2, Xnmi Oscillator and PLL Peripheral Frames 0, 1, 2 PFn 19 32-Bit CPU-Timers 0, 1General-Purpose Input/Output Gpio Multiplexer Control Peripherals Register Map Serial Port Peripherals Peripheral Frame 0 Registers1 Access TypePeripheral Frame 1 Registers1 Name Address Range Interrupts Device Emulation Registers10. Peripheral Frame 2 Registers1 11. Device Emulation Registers External and PIE Interrupt Sources INT1 INT2 INT11 INT12 MUXIntm 13. PIE Configuration and Control Registers External Interrupts14. External Interrupt Registers System Control OSC and PLL Block 15. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 Crystal External Clock Signal Toggling 0 −V DD PLL Mode Remarks Pllstsclkindiv Sysclkout Clkin 17. Possible PLL Configuration ModesPLL-Based Clock Module 16. Pllcr Register Bit Definitions Loss of Input Clock Watchdog Block 18. Low-Power Modes Low-Power Modes BlockLPMCR010 Oscclk Clkin Sysclkout Tddrhtddr 32-Bit CPU-Timers 0/1/2Prdhprd Pschpsc TCR.4 CPU-Timers 0, 1, 2 Configuration and Control Registers Enhanced PWM Modules ePWM1/2/3/4/5/6 EPWM Control and Status Registers EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 Size#SHADOW CTR = Zero Enhanced CAP Modules eCAP1/2/3/4 Hi-Resolution PWM Hrpwm Ctrovf OVF CtrphsRST CTR=PRD CTR=CMP ECAP Control and Status Registers ECAP1 ECAP2 ECAP3 ECAP4Size Description Enhanced QEP Modules eQEP1/2 EQEP1 EQEP2 EQEP Control and Status RegistersRegister Description Address #SHADOW Enhanced Analog-to-Digital Converter ADC Module ADCINA0 Sysclkout DSP Adcenclk Halt HspclkADCINA7 ADCINB0 ADCINB7 ADCINB70 ADCINA70Adclo Adcrefin Adcresext ADC Connections if the ADC Is Not Used ADC Registers1 ADC Registers Peripherals TMS320F2802, TMS320F2801, TMS320C2802 TMS320F2809, TMS320F2808, TMS320F2806SN65HVD23x Can Bus 11. eCAN-A Memory Map 12. eCAN-B Memory Map Register Name Can Register Map1ECAN-A ECAN-B Size Description Address Serial Communications Interface SCI Modules SCI-A, SCI-B SCI-B Registers1 SCI-A Registers1 13. Serial Communications Interface SCI Module Block Diagram When Spibrr = 3 to 11. SPI-B Registers 10. SPI-A Registers 13. SPI-D Registers 12. SPI-C Registers −−−−− 14. SPI Module Block Diagram Slave Mode Inter-Integrated Circuit I2C Gpio MUX Sdaa Scla 14. I2C-A RegistersI2CAENCLK I2C−A C28X CPU Sysclkout Sysrs Gpioxnmisel Gpiolmpsel GPIOXINT1SEL GPIOXINT2SEL 15. Gpio Registers Gpio Control Registers Eallow ProtectedGpio Data Registers not Eallow Protected GPAMUX1/2 16. F2808 Gpio MUX TableGPAMUX1 GPAMUX2 Sync Sysclkout Time between samples GPyCTRL Reg GPIOx Device and Development Support Tool Nomenclature Software Development ToolsHardware Development Tools TMS Temperature RangePrefix Device Family TMS320x280x, 2801x Peripheral Selection Guide Documentation SupportLiterature Peripheral Guide Application Programming Interface API Reference TMS320C28x TMS320x281x to TMS320x2833x or 2823x Migration Overview Application Reports and SoftwareTMS320x280x to TMS320x2833x or 2823x Migration Overview C28x FPU Primer Software SPRA820 Device Support Absolute Maximum Ratings1 Electrical Specifications Recommended Operating Conditions Electrical CharacteristicsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX Unit Sysclkout Current Consumption TYP5 MAX6 SCI-A SPI-A ADC TYP4 MAX5 Peripheral DD Current Module Reducing Current ConsumptionADC I2C SCI SPI Current Consumption Graphs Total PowerIDD IDDA18 Iddio Typical Operational Current Versus Frequency C280x Typical Operational Power Versus Frequency C280x EMU0 EMU1 Trst TMS TDI TDO TCK DSP GND Tckret Jtagheader Emulator Connection Without Signal Buffering for the DSP General Notes on Timing Parameters Timing Parameter SymbologyTest Load Circuit 85 pF TMS320x280x Clock Table and Nomenclature 100-MHz Devices Device Clock Table XCLKIN1 Timing Requirements PLL Enabled Clock Requirements and Characteristics10. XCLKIN1 Timing Requirements PLL Disabled Input Clock Frequency Power Management and Supervisory Circuit Solutions Power Sequencing12. Power Management and Supervisory Circuit Solutions Xclkina Xclkoutb OSCCLK/8A Xclkout 13. Reset XRS Timing Requirements Xclkout XRSOSCCLK/8 General-Purpose Input/Output Gpio 14. General-Purpose Output Switching CharacteristicsGpio Output Timing Sysclkout Oscclk OSCCLK/2 Gpio Input Timing Gpio Signal GPxQSELn = 1,0 6 samplesSysclkout Qualprd = 1 SYSCLKOUT/2 Output From Qualifier Sampling Window Width for Input Signals CaseGPIOxn 16. Idle Mode Timing Requirements1 Low-Power Mode Wakeup Timing17. Idle Mode Switching Characteristics1 Address/Data Internal 19. Standby Mode Switching Characteristics 18. Standby Mode Timing RequirementsTest Conditions MIN NOM MAX Unit Xclkin Xclkout Standby 21. Halt Mode Switching Characteristics 20. Halt Mode Timing Requirements Enhanced Control Peripherals 23. ePWM Switching CharacteristicsEnhanced Pulse Width Modulator ePWM Timing Trip-Zone Input Timing 29. eQEP Switching Characteristics 27. eCAP Switching Characteristics26. Enhanced Capture eCAP Timing Requirement1 MIN TYP MAX Unit External Interrupt Timing 32. External Interrupt Switching Characteristics1Parameter Adcsocbo Serial Peripheral Interface SPI Master Mode Timing 10.4 I2C Electrical Specification and Timing33. I2C Timing Vddio 34. SPI Master Mode External Timing Clock Phase = 0 1 2 3 4 Spisimo Spisomi Master In Data Must Be ValidSpistea 35. SPI Master Mode External Timing Clock Phase = 1 1 2 3 4 Clock polarity = SpiclkData Valid Spisomi 36. SPI Slave Mode External Timing Clock Phase = 01 2 3 4 SPI Slave Mode Timing Spisimo Data Must Be Valid 37. SPI Slave Mode External Timing Clock Phase = 11 2 On-Chip Analog-to-Digital Converter ADC Power-Up Control Bit Timing Converter Analog InputsConversion Modes ADCIN0 Sequential Sampling Mode Single-Channel Smode = AT 12.5 MHz Sample n Sample n +ADC Clock Remarks Simultaneous Sampling Mode Dual-Channel Smode = Detailed Descriptions 44. Flash Endurance for Q Temperature Material1 43. Flash Endurance for a and S Temperature Material146. Flash/OTP Access Timing Flash Timing ROM Timing C280x only 48. ROM/OTP Access TimingSysclkout ns Flash Flash Random OTP WAIT-STATE Migration Issues ADDITIONS, DELETIONS, and Modifications F280x Thermal Model 100-pin PZ Results F280x Thermal Model 100-pin GGM ResultsC280x Thermal Model 100-pin GGM Results C280x Thermal Model 100-pin PZ Results ΨJTC/W F2809 Thermal Model 100-pin PZ Results Package Type Pins Package Qty Eco Plan Lead Orderable DeviceSamples Package Qty Eco Plan Lead TMS320F2802ZGMS Active TMS320F2802ZGMA ActiveTMS320F2806GGMA Active Microstar TMS320F2806GGMS Active TMS320F2809ZGMS Active TMS320F2809ZGMA Active 10,10 20 TYP GGM S-PBGA-N10040 MAX 4145257-3/C 12/01Page Plastic Quad Flatpack PZ S-PQFP-G100 Products Applications DSPRfid