Texas Instruments TMS320F2809, TMS320F2808, TMS320C2802 ADC Power-Up Control Bit Timing

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009		www.ti.com
6.10.7.1 ADC Power-Up Control Bit Timing
	ADC Power Up Delay	ADC Ready for Conversions
PWDNBG

PWDNREF

td(BGR)

PWDNADC

td(PWD)

Request for

ADC

Conversion

Figure 6-24. ADC Power-Up Control Bit Timing

Table 6-39. ADC Power-Up Delays

	PARAMETER (1)	MIN
td(BGR)	Delay time for band gap reference to be stable. Bits 7 and 6 of the ADCTRL3
	register (ADCBGRFDN1/0) must be set to 1 before the PWDNADC bit is enabled.
td(PWD)	Delay time for power-down control to be stable. Bit delay time for band-gap	20
	reference to be stable. Bits 7 and 6 of the ADCTRL3 register (ADCBGRFDN1/0)
	must be set to 1 before the PWDNADC bit is enabled. Bit 5 of the ADCTRL3
	register (PWDNADC)must be set to 1 before any ADC conversions are initiated.

TYP MAX	UNIT
5	ms

50μs

1 ms

(1)Timings maintain compatibility to the 281x ADC module. The 280x ADC also supports driving all 3 bits at the same time and waiting td(BGR) ms before first conversion.

Table 6-40. Current Consumption for Different ADC Configurations (at 12.5-MHz ADCCLK)(1) (2)

ADC OPERATING MODE		CONDITIONS	VDDA18	VDDA3.3	UNIT
Mode A (Operational Mode):	• BG and REF enabled		30	2	mA
	•	PWD disabled
Mode B:	•	ADC clock enabled	9	0.5	mA
	• BG and REF enabled
	•	PWD enabled
Mode C:	•	ADC clock enabled	5	20	μA
	• BG and REF disabled
	•	PWD enabled
Mode D:	•	ADC clock disabled	5	15	μA
	• BG and REF disabled
	•	PWD enabled

(1)Test Conditions: SYSCLKOUT = 100 MHz ADC module clock = 12.5 MHz

ADC performing a continuous conversion of all 16 channels in Mode A

(2)VDDA18 includes current into VDD1A18 and VDD2A18. VDDA3.3 includes current into VDDA2 and VDDAIO.

126	Electrical Specifications	Copyright © 2003–2009, Texas Instruments Incorporated
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TMS320C2801 TMS320F28016 TMS320F28015