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Texas Instruments TMS320C2801, TMS320F2809 Spisimo, Spisomi Master In Data Must Be Valid, Spistea

Models: TMS320F28016 TMS320F2801 TMS320F2802 TMS320F28015 TMS320C2801 TMS320F2806 TMS320F2808 TMS320F2809 TMS320C2802

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009

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1

SPICLK (clock polarity = 0)

2

3

SPICLK (clock polarity = 1)

4

5

SPISIMO

Master Out Data Is Valid

8

9

SPISOMI Master In Data

Must Be Valid

SPISTE(A)

A.In the master mode, SPISTE goes active 0.5tc(SPC) (minimum) before valid SPI clock edge. On the trailing end of the word, the SPISTE will go inactive 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit, except that SPISTE stays active between back-to-back transmit words in both FIFO and non-FIFO modes.

Figure 6-20. SPI Master Mode External Timing (Clock Phase = 0)

120 Electrical SpecificationsCopyright © 2003–2009, Texas Instruments Incorporated

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TMS320C2801 TMS320F28016 TMS320F28015

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Texas Instruments TMS320C2801, TMS320F2809, TMS320F2808, TMS320C2802 Spisimo, Spisomi Master In Data Must Be Valid, Spistea

Contents

Data Manual ROM Gpio MUX ROM Timing C280x only Typical Operational Power Versus Frequency F2808 Warm Reset TMS320F2809, TMS320F2808, TMS320F2806 Xclkin Timing Requirements PLL Enabled Features Check forGetting Started Acquire the appropriate development toolsDownload starter software Download flash programming softwareIntroduction Hardware Features 100-MHz Devices Feature TYPE1Hardware Features 60-MHz Devices FeaturePin Assignments TMS320F2809, TMS320F2808 100-Pin PZ Lqfp Top ViewTMS320F2806 100-Pin PZ Lqfp Top View On the C280x devices, the VDD3VFL pin is Vddio TMS320F2801x 100-Pin PZ Lqfp Top View Bottom View Signal Descriptions Signal DescriptionsReset ADC SignalsCPU and I/O Power Pins Gpioa and Peripheral Signals 2 Signal Descriptions TMS320F2809, TMS320F2808, TMS320F2806 TMS320C2801, TMS320F28016, TMS320F28015GPIO33 Functional Block Diagram Protected by the CODE-SECURITY ModuleMemory Maps F2809 Memory MapF2808 Memory Map F2806 Memory Map F2802, C2802 Memory Map F2801, F28015, F28016, C2801 Memory Map Addresses of Flash Sectors in F2809 Addresses of Flash Sectors in F2808Addresses of Flash Sectors in F2806, F2802 Address Range Program and Data SpaceImpact of Using the Code Security Module Addresses of Flash Sectors in F2801, F28015, F28016Address Flash ROM Wait-states Area WAIT-STATES CommentsOTP H0 SaramBrief Descriptions 1 C28x CPUMemory Bus Harvard Bus Architecture Peripheral BusReal-Time Jtag and Analysis Flash6 ROM 7 M0, M1 SARAMsBoot ROM Boot Mode Selection8 L0, L1, H0 SARAMs Security Disclaimer Code Security Module DisclaimerLow-Power Modes Peripheral Interrupt Expansion PIE BlockExternal Interrupts XINT1, XINT2, Xnmi Oscillator and PLL19 32-Bit CPU-Timers 0, 1 Peripheral Frames 0, 1, 2 PFnGeneral-Purpose Input/Output Gpio Multiplexer Control PeripheralsSerial Port Peripherals Register MapAccess Type Peripheral Frame 0 Registers1Peripheral Frame 1 Registers1 Name Address RangeDevice Emulation Registers Interrupts10. Peripheral Frame 2 Registers1 11. Device Emulation RegistersExternal and PIE Interrupt Sources INT1 INT2 INT11 INT12 MUXIntm 13. PIE Configuration and Control Registers External Interrupts14. External Interrupt Registers System Control 15. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 OSC and PLL BlockExternal Clock Signal Toggling 0 −V DD Crystal17. Possible PLL Configuration Modes PLL Mode Remarks Pllstsclkindiv Sysclkout ClkinPLL-Based Clock Module 16. Pllcr Register Bit DefinitionsLoss of Input Clock Watchdog Block Low-Power Modes Block 18. Low-Power ModesLPMCR010 Oscclk Clkin Sysclkout32-Bit CPU-Timers 0/1/2 TddrhtddrPrdhprd Pschpsc TCR.4CPU-Timers 0, 1, 2 Configuration and Control Registers Enhanced PWM Modules ePWM1/2/3/4/5/6 EPWM Control and Status Registers EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 Size#SHADOW CTR = Zero Hi-Resolution PWM Hrpwm Enhanced CAP Modules eCAP1/2/3/4Ctrphs Ctrovf OVFRST CTR=PRD CTR=CMPECAP Control and Status Registers ECAP1 ECAP2 ECAP3 ECAP4Size Description Enhanced QEP Modules eQEP1/2 EQEP Control and Status Registers EQEP1 EQEP2Register Description Address #SHADOWEnhanced Analog-to-Digital Converter ADC Module Sysclkout DSP Adcenclk Halt Hspclk ADCINA0ADCINA7 ADCINB0 ADCINB7ADCINA70 ADCINB70Adclo AdcrefinADC Connections if the ADC Is Not Used AdcresextADC Registers ADC Registers1Peripherals TMS320F2809, TMS320F2808, TMS320F2806 TMS320F2802, TMS320F2801, TMS320C2802SN65HVD23x Can Bus11. eCAN-A Memory Map 12. eCAN-B Memory Map Can Register Map1 Register NameECAN-A ECAN-B Size Description AddressSerial Communications Interface SCI Modules SCI-A, SCI-B SCI-A Registers1 SCI-B Registers113. Serial Communications Interface SCI Module Block Diagram When Spibrr = 3 to 10. SPI-A Registers 11. SPI-B Registers12. SPI-C Registers 13. SPI-D Registers14. SPI Module Block Diagram Slave Mode −−−−−Inter-Integrated Circuit I2C 14. I2C-A Registers Gpio MUX Sdaa SclaI2CAENCLK I2C−A C28X CPU Sysclkout SysrsGpiolmpsel GPIOXINT1SEL GPIOXINT2SEL Gpioxnmisel15. Gpio Registers Gpio Control Registers Eallow ProtectedGpio Data Registers not Eallow Protected 16. F2808 Gpio MUX Table GPAMUX1/2GPAMUX1 GPAMUX2Time between samples GPyCTRL Reg GPIOx Sync SysclkoutDevice and Development Support Tool Nomenclature Software Development ToolsHardware Development Tools Temperature Range TMSPrefix Device FamilyDocumentation Support TMS320x280x, 2801x Peripheral Selection GuideLiterature Peripheral GuideTMS320C28x Application Programming Interface API ReferenceApplication Reports and Software TMS320x281x to TMS320x2833x or 2823x Migration OverviewTMS320x280x to TMS320x2833x or 2823x Migration Overview C28x FPU PrimerSPRA820 SoftwareDevice Support Electrical Specifications Absolute Maximum Ratings1Electrical Characteristics Recommended Operating ConditionsMIN NOM MAX Unit Parameter Test Conditions MIN TYP MAX UnitCurrent Consumption SysclkoutTYP5 MAX6 SCI-A SPI-A ADC TYP4 MAX5 Reducing Current Consumption Peripheral DD Current ModuleADC I2C SCI SPITotal Power Current Consumption GraphsIDD IDDA18 IddioTypical Operational Power Versus Frequency C280x Typical Operational Current Versus Frequency C280xEmulator Connection Without Signal Buffering for the DSP EMU0 EMU1 Trst TMS TDI TDO TCK DSP GND Tckret JtagheaderTiming Parameter Symbology General Notes on Timing ParametersTest Load Circuit 85 pFDevice Clock Table TMS320x280x Clock Table and Nomenclature 100-MHz DevicesClock Requirements and Characteristics XCLKIN1 Timing Requirements PLL Enabled10. XCLKIN1 Timing Requirements PLL Disabled Input Clock FrequencyPower Sequencing Power Management and Supervisory Circuit Solutions12. Power Management and Supervisory Circuit Solutions Xclkina XclkoutbXclkout OSCCLK/8A13. Reset XRS Timing Requirements Xclkout XRSOSCCLK/8 14. General-Purpose Output Switching Characteristics General-Purpose Input/Output GpioGpio Output Timing Sysclkout Oscclk OSCCLK/2Gpio Signal GPxQSELn = 1,0 6 samples Gpio Input TimingSysclkout Qualprd = 1 SYSCLKOUT/2 Output From QualifierSampling Window Width for Input Signals CaseGPIOxn Low-Power Mode Wakeup Timing 16. Idle Mode Timing Requirements117. Idle Mode Switching Characteristics1 Address/Data Internal18. Standby Mode Timing Requirements 19. Standby Mode Switching CharacteristicsTest Conditions MIN NOM MAX Unit Xclkin Xclkout Standby20. Halt Mode Timing Requirements 21. Halt Mode Switching Characteristics23. ePWM Switching Characteristics Enhanced Control PeripheralsEnhanced Pulse Width Modulator ePWM Timing Trip-Zone Input Timing27. eCAP Switching Characteristics 29. eQEP Switching Characteristics26. Enhanced Capture eCAP Timing Requirement1 MIN TYP MAX Unit32. External Interrupt Switching Characteristics1 External Interrupt TimingParameter Adcsocbo10.4 I2C Electrical Specification and Timing Serial Peripheral Interface SPI Master Mode Timing33. I2C Timing Vddio34. SPI Master Mode External Timing Clock Phase = 0 1 2 3 4 Spisimo Spisomi Master In Data Must Be ValidSpistea 35. SPI Master Mode External Timing Clock Phase = 1 1 2 3 4 Spiclk Clock polarity =Data Valid SpisomiSPI Slave Mode Timing 36. SPI Slave Mode External Timing Clock Phase = 01 2 3 437. SPI Slave Mode External Timing Clock Phase = 11 2 Spisimo Data Must Be ValidOn-Chip Analog-to-Digital Converter ADC Power-Up Control Bit Timing Analog Inputs ConverterConversion Modes ADCIN0Sequential Sampling Mode Single-Channel Smode = AT 12.5 MHz Sample n Sample n +ADC Clock Remarks Simultaneous Sampling Mode Dual-Channel Smode = Detailed Descriptions 43. Flash Endurance for a and S Temperature Material1 44. Flash Endurance for Q Temperature Material146. Flash/OTP Access Timing Flash Timing48. ROM/OTP Access Timing ROM Timing C280x onlySysclkout ns Flash Flash Random OTP WAIT-STATEMigration Issues ADDITIONS, DELETIONS, and Modifications F280x Thermal Model 100-pin GGM Results F280x Thermal Model 100-pin PZ ResultsC280x Thermal Model 100-pin GGM Results C280x Thermal Model 100-pin PZ ResultsF2809 Thermal Model 100-pin PZ Results ΨJTC/WPackage Type Pins Package Qty Eco Plan Lead Orderable DeviceSamples Package Qty Eco Plan Lead TMS320F2802ZGMA Active TMS320F2802ZGMS ActiveTMS320F2806GGMA Active Microstar TMS320F2806GGMS ActiveTMS320F2809ZGMA Active TMS320F2809ZGMS ActiveGGM S-PBGA-N100 10,10 20 TYP40 MAX 4145257-3/C 12/01Page PZ S-PQFP-G100 Plastic Quad FlatpackProducts Applications DSPRfid