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Texas Instruments TMS320F28016 Ctrphs, Ctrovf OVF, Rst, Ctr=Prd Ctr=Cmp, LD1 Select, CAP1

Models: TMS320F28016 TMS320F2801 TMS320F2802 TMS320F28015 TMS320C2801 TMS320F2806 TMS320F2808 TMS320F2809 TMS320C2802

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							TMS320F2809, TMS320F2808, TMS320F2806
							TMS320F2802, TMS320F2801, TMS320C2802
							TMS320C2801, TMS320F28016, TMS320F28015
www.ti.com							SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009
			CTRPHS				APWM mode
SYNCIn	SYNC	(phase register−32 bit)				CTR_OVF	APWM mode
	SYNC				OVF	CTR_OVF	CTR [0−31]

SYNCOut			TSCTR					PWM
SYNCOut			(counter−32	bit)				PWM
			(counter−32	bit)	RST	Delta−mode	PRD [0−31]	compare
						Delta−mode	PRD [0−31]	compare
								logic
							CMP [0−31]	logic
							CMP [0−31]
			32
					CTR [0−31]		CTR=PRD
					CTR [0−31]		CTR=CMP
			32				CTR=CMP
			32		PRD [0−31]
					PRD [0−31]
32						LD1		SELECT	eCAPx
			CAP1		LD		Polarity	SELECT


			(APRD active)				select
			(APRD active)				select	MODE
	shadow				CMP [0−31]			MODE
		APRD	32
			32
			32
32			CAP2		LD	LD2	Polarity
			CAP2			LD2	Polarity
			(ACMP active)				select
			(ACMP active)				select
			32	ACMP		Event		Event
			32	ACMP		qualifier		Event
				shadow		qualifier		Pre-scale
				shadow				Pre-scale
32			CAP3			LD3	Polarity
32					LD		select

			(APRD shadow)
			(APRD shadow)
32			CAP4		LD	LD4	Polarity
			(ACMP shadow)		LD		select
			(ACMP shadow)				select

to PIE

Interrupt

Trigger

and Flag control

4

Capture events

CEVT[1:4]

CTR_OVF

CTR=PRD

CTR=CMP

4

Continuous /

Oneshot

Capture Control

Figure 4-5. eCAP Functional Block Diagram

Copyright © 2003–2009, Texas Instruments Incorporated

Peripherals

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TMS320C2801 TMS320F28016 TMS320F28015

Image 59

Texas Instruments TMS320F28016 Ctrphs, Ctrovf OVF, Rst, Ctr=Prd Ctr=Cmp, LD1 Select, CAP1, Aprd CAP2 LD2, CAP3 LD3

Contents

Data Manual ROM Gpio MUX ROM Timing C280x only Typical Operational Power Versus Frequency F2808 Warm Reset TMS320F2809, TMS320F2808, TMS320F2806 Xclkin Timing Requirements PLL Enabled Check for Features Download flash programming software Getting StartedAcquire the appropriate development tools Download starter software Introduction Feature TYPE1 Hardware Features 100-MHz Devices Feature Hardware Features 60-MHz Devices TMS320F2809, TMS320F2808 100-Pin PZ Lqfp Top View Pin Assignments TMS320F2806 100-Pin PZ Lqfp Top View On the C280x devices, the VDD3VFL pin is Vddio TMS320F2801x 100-Pin PZ Lqfp Top View Bottom View Signal Descriptions Signal Descriptions CPU and I/O Power Pins ResetADC Signals Gpioa and Peripheral Signals 2 Signal Descriptions TMS320C2801, TMS320F28016, TMS320F28015 TMS320F2809, TMS320F2808, TMS320F2806 GPIO33 Protected by the CODE-SECURITY Module Functional Block Diagram F2809 Memory Map Memory Maps F2808 Memory Map F2806 Memory Map F2802, C2802 Memory Map F2801, F28015, F28016, C2801 Memory Map Address Range Program and Data Space Addresses of Flash Sectors in F2809Addresses of Flash Sectors in F2808 Addresses of Flash Sectors in F2806, F2802 Address Flash ROM Impact of Using the Code Security ModuleAddresses of Flash Sectors in F2801, F28015, F28016 H0 Saram Wait-statesArea WAIT-STATES Comments OTP Peripheral Bus Brief Descriptions1 C28x CPU Memory Bus Harvard Bus Architecture 7 M0, M1 SARAMs Real-Time Jtag and AnalysisFlash 6 ROM 8 L0, L1, H0 SARAMs Boot ROMBoot Mode Selection Disclaimer Code Security Module Disclaimer Security Oscillator and PLL Low-Power ModesPeripheral Interrupt Expansion PIE Block External Interrupts XINT1, XINT2, Xnmi Control Peripherals 19 32-Bit CPU-Timers 0, 1Peripheral Frames 0, 1, 2 PFn General-Purpose Input/Output Gpio Multiplexer Register Map Serial Port Peripherals Name Address Range Access TypePeripheral Frame 0 Registers1 Peripheral Frame 1 Registers1 11. Device Emulation Registers Device Emulation RegistersInterrupts 10. Peripheral Frame 2 Registers1 External and PIE Interrupt Sources Intm INT1 INT2 INT11 INT12MUX 14. External Interrupt Registers 13. PIE Configuration and Control RegistersExternal Interrupts System Control OSC and PLL Block 15. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 Crystal External Clock Signal Toggling 0 −V DD 16. Pllcr Register Bit Definitions 17. Possible PLL Configuration ModesPLL Mode Remarks Pllstsclkindiv Sysclkout Clkin PLL-Based Clock Module Loss of Input Clock Watchdog Block Oscclk Clkin Sysclkout Low-Power Modes Block18. Low-Power Modes LPMCR010 Pschpsc TCR.4 32-Bit CPU-Timers 0/1/2Tddrhtddr Prdhprd CPU-Timers 0, 1, 2 Configuration and Control Registers Enhanced PWM Modules ePWM1/2/3/4/5/6 #SHADOW EPWM Control and Status RegistersEPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 Size CTR = Zero Enhanced CAP Modules eCAP1/2/3/4 Hi-Resolution PWM Hrpwm CTR=PRD CTR=CMP CtrphsCtrovf OVF RST Size Description ECAP Control and Status RegistersECAP1 ECAP2 ECAP3 ECAP4 Enhanced QEP Modules eQEP1/2 Address #SHADOW EQEP Control and Status RegistersEQEP1 EQEP2 Register Description Enhanced Analog-to-Digital Converter ADC Module ADCINB0 ADCINB7 Sysclkout DSP Adcenclk Halt HspclkADCINA0 ADCINA7 Adcrefin ADCINA70ADCINB70 Adclo Adcresext ADC Connections if the ADC Is Not Used ADC Registers1 ADC Registers Peripherals Can Bus TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802 SN65HVD23x 11. eCAN-A Memory Map 12. eCAN-B Memory Map Size Description Address Can Register Map1Register Name ECAN-A ECAN-B Serial Communications Interface SCI Modules SCI-A, SCI-B SCI-B Registers1 SCI-A Registers1 13. Serial Communications Interface SCI Module Block Diagram When Spibrr = 3 to 11. SPI-B Registers 10. SPI-A Registers 13. SPI-D Registers 12. SPI-C Registers −−−−− 14. SPI Module Block Diagram Slave Mode Inter-Integrated Circuit I2C Sysrs 14. I2C-A RegistersGpio MUX Sdaa Scla I2CAENCLK I2C−A C28X CPU Sysclkout Gpioxnmisel Gpiolmpsel GPIOXINT1SEL GPIOXINT2SEL Gpio Data Registers not Eallow Protected 15. Gpio RegistersGpio Control Registers Eallow Protected GPAMUX2 16. F2808 Gpio MUX TableGPAMUX1/2 GPAMUX1 Sync Sysclkout Time between samples GPyCTRL Reg GPIOx Hardware Development Tools Device and Development Support Tool NomenclatureSoftware Development Tools Device Family Temperature RangeTMS Prefix Peripheral Guide Documentation SupportTMS320x280x, 2801x Peripheral Selection Guide Literature Application Programming Interface API Reference TMS320C28x C28x FPU Primer Application Reports and SoftwareTMS320x281x to TMS320x2833x or 2823x Migration Overview TMS320x280x to TMS320x2833x or 2823x Migration Overview Software SPRA820 Device Support Absolute Maximum Ratings1 Electrical Specifications Parameter Test Conditions MIN TYP MAX Unit Electrical CharacteristicsRecommended Operating Conditions MIN NOM MAX Unit Sysclkout Current Consumption TYP5 MAX6 SCI-A SPI-A ADC TYP4 MAX5 SCI SPI Reducing Current ConsumptionPeripheral DD Current Module ADC I2C Iddio Total PowerCurrent Consumption Graphs IDD IDDA18 Typical Operational Current Versus Frequency C280x Typical Operational Power Versus Frequency C280x EMU0 EMU1 Trst TMS TDI TDO TCK DSP GND Tckret Jtagheader Emulator Connection Without Signal Buffering for the DSP 85 pF Timing Parameter SymbologyGeneral Notes on Timing Parameters Test Load Circuit TMS320x280x Clock Table and Nomenclature 100-MHz Devices Device Clock Table Input Clock Frequency Clock Requirements and CharacteristicsXCLKIN1 Timing Requirements PLL Enabled 10. XCLKIN1 Timing Requirements PLL Disabled Xclkina Xclkoutb Power SequencingPower Management and Supervisory Circuit Solutions 12. Power Management and Supervisory Circuit Solutions OSCCLK/8A Xclkout OSCCLK/8 13. Reset XRS Timing RequirementsXclkout XRS Sysclkout Oscclk OSCCLK/2 14. General-Purpose Output Switching CharacteristicsGeneral-Purpose Input/Output Gpio Gpio Output Timing Output From Qualifier Gpio Signal GPxQSELn = 1,0 6 samplesGpio Input Timing Sysclkout Qualprd = 1 SYSCLKOUT/2 GPIOxn Sampling Window Width for Input SignalsCase Address/Data Internal Low-Power Mode Wakeup Timing16. Idle Mode Timing Requirements1 17. Idle Mode Switching Characteristics1 Xclkin Xclkout Standby 18. Standby Mode Timing Requirements19. Standby Mode Switching Characteristics Test Conditions MIN NOM MAX Unit 21. Halt Mode Switching Characteristics 20. Halt Mode Timing Requirements Trip-Zone Input Timing 23. ePWM Switching CharacteristicsEnhanced Control Peripherals Enhanced Pulse Width Modulator ePWM Timing MIN TYP MAX Unit 27. eCAP Switching Characteristics29. eQEP Switching Characteristics 26. Enhanced Capture eCAP Timing Requirement1 Adcsocbo 32. External Interrupt Switching Characteristics1External Interrupt Timing Parameter Vddio 10.4 I2C Electrical Specification and TimingSerial Peripheral Interface SPI Master Mode Timing 33. I2C Timing 34. SPI Master Mode External Timing Clock Phase = 0 1 2 3 4 Spistea SpisimoSpisomi Master In Data Must Be Valid 35. SPI Master Mode External Timing Clock Phase = 1 1 2 3 4 Spisomi SpiclkClock polarity = Data Valid 36. SPI Slave Mode External Timing Clock Phase = 01 2 3 4 SPI Slave Mode Timing Spisimo Data Must Be Valid 37. SPI Slave Mode External Timing Clock Phase = 11 2 On-Chip Analog-to-Digital Converter ADC Power-Up Control Bit Timing ADCIN0 Analog InputsConverter Conversion Modes ADC Clock Remarks Sequential Sampling Mode Single-Channel Smode =AT 12.5 MHz Sample n Sample n + Simultaneous Sampling Mode Dual-Channel Smode = Detailed Descriptions Flash Timing 43. Flash Endurance for a and S Temperature Material144. Flash Endurance for Q Temperature Material1 46. Flash/OTP Access Timing Flash Flash Random OTP WAIT-STATE 48. ROM/OTP Access TimingROM Timing C280x only Sysclkout ns Migration Issues ADDITIONS, DELETIONS, and Modifications C280x Thermal Model 100-pin PZ Results F280x Thermal Model 100-pin GGM ResultsF280x Thermal Model 100-pin PZ Results C280x Thermal Model 100-pin GGM Results ΨJTC/W F2809 Thermal Model 100-pin PZ Results Samples Package Type Pins Package Qty Eco Plan LeadOrderable Device Package Qty Eco Plan Lead Microstar TMS320F2806GGMS Active TMS320F2802ZGMA ActiveTMS320F2802ZGMS Active TMS320F2806GGMA Active TMS320F2809ZGMS Active TMS320F2809ZGMA Active 4145257-3/C 12/01 GGM S-PBGA-N10010,10 20 TYP 40 MAXPage Plastic Quad Flatpack PZ S-PQFP-G100 Rfid Products ApplicationsDSP