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Texas Instruments TMS320C2801 Emulator Connection Without Signal Buffering for the DSP

Models: TMS320F28016 TMS320F2801 TMS320F2802 TMS320F28015 TMS320C2801 TMS320F2806 TMS320F2808 TMS320F2809 TMS320C2802

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TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009

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6.5Emulator Connection Without Signal Buffering for the DSP

Figure 6-5shows the connection between the DSP and JTAG header for a single-processor configuration. If the distance between the JTAG header and the DSP is greater than 6 inches, the emulation signals must be buffered. If the distance is less than 6 inches, buffering is typically not needed. Figure 6-5shows the simpler, no-buffering situation. For the pullup/pulldown resistor values, see the pin description section.

6INCHESORLESS

VDDIO								VDDIO

EMU0

EMU1

TRST

TMS

TDI

TDO

TCK

DSP

				13					5
				13					5
					EMU0			PD
				14	EMU0			PD
				14
					EMU1				4
				2	EMU1
				2
					TRST			GND
	1				TRST			GND	6
	1								6
					TMS			GND
	3				TMS			GND	8
	3								8
					TDI			GND
	7				TDI			GND	10
	7								10
					TDO			GND
	11				TDO			GND	12
	11								12
					TCK			GND
				9	TCK			GND
				9
					TCK_RET
					TCK_RET

JTAGHEADER

Figure 6-5. Emulator Connection Without Signal Buffering for the DSP

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Electrical Specifications

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TMS320C2801 TMS320F28016 TMS320F28015

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Texas Instruments TMS320C2801, TMS320F2809, TMS320F2808 Emulator Connection Without Signal Buffering for the DSP

Contents

Data Manual ROM Gpio MUX ROM Timing C280x only Typical Operational Power Versus Frequency F2808 Warm Reset TMS320F2809, TMS320F2808, TMS320F2806 Xclkin Timing Requirements PLL Enabled Features Check forDownload starter software Getting StartedAcquire the appropriate development tools Download flash programming softwareIntroduction Hardware Features 100-MHz Devices Feature TYPE1Hardware Features 60-MHz Devices FeaturePin Assignments TMS320F2809, TMS320F2808 100-Pin PZ Lqfp Top ViewTMS320F2806 100-Pin PZ Lqfp Top View On the C280x devices, the VDD3VFL pin is Vddio TMS320F2801x 100-Pin PZ Lqfp Top View Bottom View Signal Descriptions Signal DescriptionsReset ADC SignalsCPU and I/O Power Pins Gpioa and Peripheral Signals 2 Signal Descriptions TMS320F2809, TMS320F2808, TMS320F2806 TMS320C2801, TMS320F28016, TMS320F28015GPIO33 Functional Block Diagram Protected by the CODE-SECURITY ModuleMemory Maps F2809 Memory MapF2808 Memory Map F2806 Memory Map F2802, C2802 Memory Map F2801, F28015, F28016, C2801 Memory Map Addresses of Flash Sectors in F2806, F2802 Addresses of Flash Sectors in F2809Addresses of Flash Sectors in F2808 Address Range Program and Data SpaceImpact of Using the Code Security Module Addresses of Flash Sectors in F2801, F28015, F28016Address Flash ROM OTP Wait-statesArea WAIT-STATES Comments H0 SaramMemory Bus Harvard Bus Architecture Brief Descriptions1 C28x CPU Peripheral Bus6 ROM Real-Time Jtag and AnalysisFlash 7 M0, M1 SARAMsBoot ROM Boot Mode Selection8 L0, L1, H0 SARAMs Security Disclaimer Code Security Module DisclaimerExternal Interrupts XINT1, XINT2, Xnmi Low-Power ModesPeripheral Interrupt Expansion PIE Block Oscillator and PLLGeneral-Purpose Input/Output Gpio Multiplexer 19 32-Bit CPU-Timers 0, 1Peripheral Frames 0, 1, 2 PFn Control PeripheralsSerial Port Peripherals Register MapPeripheral Frame 1 Registers1 Access TypePeripheral Frame 0 Registers1 Name Address Range10. Peripheral Frame 2 Registers1 Device Emulation RegistersInterrupts 11. Device Emulation RegistersExternal and PIE Interrupt Sources INT1 INT2 INT11 INT12 MUXIntm 13. PIE Configuration and Control Registers External Interrupts14. External Interrupt Registers System Control 15. PLL, Clocking, Watchdog, and Low-Power Mode Registers1 OSC and PLL BlockExternal Clock Signal Toggling 0 −V DD CrystalPLL-Based Clock Module 17. Possible PLL Configuration ModesPLL Mode Remarks Pllstsclkindiv Sysclkout Clkin 16. Pllcr Register Bit DefinitionsLoss of Input Clock Watchdog Block LPMCR010 Low-Power Modes Block18. Low-Power Modes Oscclk Clkin SysclkoutPrdhprd 32-Bit CPU-Timers 0/1/2Tddrhtddr Pschpsc TCR.4CPU-Timers 0, 1, 2 Configuration and Control Registers Enhanced PWM Modules ePWM1/2/3/4/5/6 EPWM Control and Status Registers EPWM1 EPWM2 EPWM3 EPWM4 EPWM5 EPWM6 Size#SHADOW CTR = Zero Hi-Resolution PWM Hrpwm Enhanced CAP Modules eCAP1/2/3/4RST CtrphsCtrovf OVF CTR=PRD CTR=CMPECAP Control and Status Registers ECAP1 ECAP2 ECAP3 ECAP4Size Description Enhanced QEP Modules eQEP1/2 Register Description EQEP Control and Status RegistersEQEP1 EQEP2 Address #SHADOWEnhanced Analog-to-Digital Converter ADC Module ADCINA7 Sysclkout DSP Adcenclk Halt HspclkADCINA0 ADCINB0 ADCINB7Adclo ADCINA70ADCINB70 AdcrefinADC Connections if the ADC Is Not Used AdcresextADC Registers ADC Registers1Peripherals SN65HVD23x TMS320F2809, TMS320F2808, TMS320F2806TMS320F2802, TMS320F2801, TMS320C2802 Can Bus11. eCAN-A Memory Map 12. eCAN-B Memory Map ECAN-A ECAN-B Can Register Map1Register Name Size Description AddressSerial Communications Interface SCI Modules SCI-A, SCI-B SCI-A Registers1 SCI-B Registers113. Serial Communications Interface SCI Module Block Diagram When Spibrr = 3 to 10. SPI-A Registers 11. SPI-B Registers12. SPI-C Registers 13. SPI-D Registers14. SPI Module Block Diagram Slave Mode −−−−−Inter-Integrated Circuit I2C I2CAENCLK I2C−A C28X CPU Sysclkout 14. I2C-A RegistersGpio MUX Sdaa Scla SysrsGpiolmpsel GPIOXINT1SEL GPIOXINT2SEL Gpioxnmisel15. Gpio Registers Gpio Control Registers Eallow ProtectedGpio Data Registers not Eallow Protected GPAMUX1 16. F2808 Gpio MUX TableGPAMUX1/2 GPAMUX2Time between samples GPyCTRL Reg GPIOx Sync SysclkoutDevice and Development Support Tool Nomenclature Software Development ToolsHardware Development Tools Prefix Temperature RangeTMS Device FamilyLiterature Documentation SupportTMS320x280x, 2801x Peripheral Selection Guide Peripheral GuideTMS320C28x Application Programming Interface API ReferenceTMS320x280x to TMS320x2833x or 2823x Migration Overview Application Reports and SoftwareTMS320x281x to TMS320x2833x or 2823x Migration Overview C28x FPU PrimerSPRA820 SoftwareDevice Support Electrical Specifications Absolute Maximum Ratings1MIN NOM MAX Unit Electrical CharacteristicsRecommended Operating Conditions Parameter Test Conditions MIN TYP MAX UnitCurrent Consumption SysclkoutTYP5 MAX6 SCI-A SPI-A ADC TYP4 MAX5 ADC I2C Reducing Current ConsumptionPeripheral DD Current Module SCI SPIIDD IDDA18 Total PowerCurrent Consumption Graphs IddioTypical Operational Power Versus Frequency C280x Typical Operational Current Versus Frequency C280xEmulator Connection Without Signal Buffering for the DSP EMU0 EMU1 Trst TMS TDI TDO TCK DSP GND Tckret JtagheaderTest Load Circuit Timing Parameter SymbologyGeneral Notes on Timing Parameters 85 pFDevice Clock Table TMS320x280x Clock Table and Nomenclature 100-MHz Devices10. XCLKIN1 Timing Requirements PLL Disabled Clock Requirements and CharacteristicsXCLKIN1 Timing Requirements PLL Enabled Input Clock Frequency12. Power Management and Supervisory Circuit Solutions Power SequencingPower Management and Supervisory Circuit Solutions Xclkina XclkoutbXclkout OSCCLK/8A13. Reset XRS Timing Requirements Xclkout XRSOSCCLK/8 Gpio Output Timing 14. General-Purpose Output Switching CharacteristicsGeneral-Purpose Input/Output Gpio Sysclkout Oscclk OSCCLK/2Sysclkout Qualprd = 1 SYSCLKOUT/2 Gpio Signal GPxQSELn = 1,0 6 samplesGpio Input Timing Output From QualifierSampling Window Width for Input Signals CaseGPIOxn 17. Idle Mode Switching Characteristics1 Low-Power Mode Wakeup Timing16. Idle Mode Timing Requirements1 Address/Data InternalTest Conditions MIN NOM MAX Unit 18. Standby Mode Timing Requirements19. Standby Mode Switching Characteristics Xclkin Xclkout Standby20. Halt Mode Timing Requirements 21. Halt Mode Switching CharacteristicsEnhanced Pulse Width Modulator ePWM Timing 23. ePWM Switching CharacteristicsEnhanced Control Peripherals Trip-Zone Input Timing26. Enhanced Capture eCAP Timing Requirement1 27. eCAP Switching Characteristics29. eQEP Switching Characteristics MIN TYP MAX UnitParameter 32. External Interrupt Switching Characteristics1External Interrupt Timing Adcsocbo33. I2C Timing 10.4 I2C Electrical Specification and TimingSerial Peripheral Interface SPI Master Mode Timing Vddio34. SPI Master Mode External Timing Clock Phase = 0 1 2 3 4 Spisimo Spisomi Master In Data Must Be ValidSpistea 35. SPI Master Mode External Timing Clock Phase = 1 1 2 3 4 Data Valid SpiclkClock polarity = SpisomiSPI Slave Mode Timing 36. SPI Slave Mode External Timing Clock Phase = 01 2 3 437. SPI Slave Mode External Timing Clock Phase = 11 2 Spisimo Data Must Be ValidOn-Chip Analog-to-Digital Converter ADC Power-Up Control Bit Timing Conversion Modes Analog InputsConverter ADCIN0Sequential Sampling Mode Single-Channel Smode = AT 12.5 MHz Sample n Sample n +ADC Clock Remarks Simultaneous Sampling Mode Dual-Channel Smode = Detailed Descriptions 46. Flash/OTP Access Timing 43. Flash Endurance for a and S Temperature Material144. Flash Endurance for Q Temperature Material1 Flash TimingSysclkout ns 48. ROM/OTP Access TimingROM Timing C280x only Flash Flash Random OTP WAIT-STATEMigration Issues ADDITIONS, DELETIONS, and Modifications C280x Thermal Model 100-pin GGM Results F280x Thermal Model 100-pin GGM ResultsF280x Thermal Model 100-pin PZ Results C280x Thermal Model 100-pin PZ ResultsF2809 Thermal Model 100-pin PZ Results ΨJTC/WPackage Type Pins Package Qty Eco Plan Lead Orderable DeviceSamples Package Qty Eco Plan Lead TMS320F2806GGMA Active TMS320F2802ZGMA ActiveTMS320F2802ZGMS Active Microstar TMS320F2806GGMS ActiveTMS320F2809ZGMA Active TMS320F2809ZGMS Active40 MAX GGM S-PBGA-N10010,10 20 TYP 4145257-3/C 12/01Page PZ S-PQFP-G100 Plastic Quad FlatpackProducts Applications DSPRfid