TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009

www.ti.com

6.9.2GPIO - Input Timing

(A)

GPIO Signal

GPxQSELn = 1,0 (6 samples)

1

1

0

0

0

0

0

0

0

1

0

0

0

1

1

1

1

1

1

1

1

1

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tw(SP)

 

 

 

 

 

 

 

Sampling Period determined

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

tw(IQSW)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

by GPxCTRL[QUALPRD](B)

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Sampling Window (SYSCLKOUT cycle * 2 * QUALPRD) * 5(C))

SYSCLKOUT

QUALPRD = 1 (SYSCLKOUT/2)

(D)

Output From

Qualifier

A.This glitch will be ignored by the input qualifier. The QUALPRD bit field specifies the qualification sampling period. It can vary from 00 to 0xFF. If QUALPRD = 00, then the sampling period is 1 SYSCLKOUT cycle. For any other value "n", the qualification sampling period in 2n SYSCLKOUT cycles (i.e., at every 2n SYSCLKOUT cycles, the GPIO pin will be sampled).

B.The qualification period selected via the GPxCTRL register applies to groups of 8 GPIO pins.

C.The qualification block can take either three or six samples. The GPxQSELn Register selects which sample mode is used.

D.In the example shown, for the qualifier to detect the change, the input should be stable for 10 SYSCLKOUT cycles or greater. In other words, the inputs should be stable for (5 x QUALPRD x 2) SYSCLKOUT cycles. This would ensure 5 sampling periods for detection to occur. Since external signals are driven asynchronously, an 13-SYSCLKOUT-wide pulse ensures reliable recognition.

Figure 6-12. Sampling Mode

Table 6-15. General-Purpose Input Timing Requirements

 

 

 

 

 

MIN

MAX

UNIT

 

 

 

 

 

 

 

 

tw(SP)

Sampling period

QUALPRD = 0

 

 

1tc(SCO)

 

cycles

QUALPRD ≠ 0

2tc(SCO) * QUALPRD

 

cycles

 

 

 

t

Input qualifier sampling window

 

t

w(SP)

* (n(1) – 1)

 

cycles

w(IQSW)

 

 

 

 

 

 

(2)

 

Synchronous mode

 

 

2tc(SCO)

 

cycles

tw(GPI)

Pulse duration, GPIO low/high

With input qualifier

tw(IQSW) + tw(SP) + 1tc(SCO)

 

cycles

 

 

 

(1)"n" represents the number of qualification samples as defined by GPxQSELn register.

(2)For tw(GPI), pulse width is measured from VIL to VIL for an active low signal and VIH to VIH for an active high signal.

110

Electrical Specifications

Copyright © 2003–2009, Texas Instruments Incorporated

 

 

Submit Documentation Feedback

Product Folder Link(s): TMS320F2809 TMS320F2808 TMS320F2806 TMS320F2802 TMS320F2801 TMS320C2802

TMS320C2801 TMS320F28016 TMS320F28015

Page 110
Image 110
Texas Instruments TMS320C2802 Gpio Input Timing, Gpio Signal GPxQSELn = 1,0 6 samples, Sysclkout Qualprd = 1 SYSCLKOUT/2