Texas Instruments TMS320F28015, TMS320F2809 SPI Slave Mode External Timing Clock Phase = 11 2

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009www.ti.com

		Table 6-37. SPI Slave Mode External Timing (Clock Phase = 1)(1) (2) (3)			(4)
NO.				MIN	MAX	UNIT
12	tc(SPC)S		Cycle time, SPICLK	8tc(LCO)		ns
13	tw(SPCH)S		Pulse duration, SPICLK high (clock polarity = 0)	0.5tc(SPC)S – 10	0.5tc(SPC)S	ns
	tw(SPCL)S		Pulse duration, SPICLK low (clock polarity = 1)	0.5tc(SPC)S – 10	0.5tc(SPC) S
14	tw(SPCL)S		Pulse duration, SPICLK low (clock polarity = 0)	0.5tc(SPC)S – 10	0.5tc(SPC) S	ns
	tw(SPCH)S		Pulse duration, SPICLK high (clock polarity = 1)	0.5tc(SPC)S – 10	0.5tc(SPC)S
	tsu(SOMI-SPCH)S		Setup time, SPISOMI before SPICLK high (clock polarity = 0)	0.125tc(SPC)S
17	tsu(SOMI-SPCL)S		Setup time, SPISOMI before SPICLK low	0.125tc(SPC)S		ns
			(clock polarity = 1)
	tv(SPCL-SOMI)S		Valid time, SPISOMI data valid after SPICLK low	0.75tc(SPC)S
18			(clock polarity = 1)			ns
	tv(SPCH-SOMI)S		Valid time, SPISOMI data valid after SPICLK high	0.75tc(SPC) S
			(clock polarity = 0)
21	tsu(SIMO-SPCH)S		Setup time, SPISIMO before SPICLK high (clock polarity = 0)	35		ns
	tsu(SIMO-SPCL)S		Setup time, SPISIMO before SPICLK low (clock polarity = 1)	35
	tv(SPCH-SIMO)S		Valid time, SPISIMO data valid after SPICLK high	0.5tc(SPC)S – 10
22			(clock polarity = 0)			ns
	tv(SPCL-SIMO)S		Valid time, SPISIMO data valid after SPICLK low	0.5tc(SPC)S – 10
			(clock polarity = 1)

(1)The MASTER / SLAVE bit (SPICTL.2) is cleared and the CLOCK PHASE bit (SPICTL.3) is cleared.

(2)tc(SPC) = SPI clock cycle time = LSPCLK/4 or LSPCLK/(SPIBRR + 1)

(3)Internal clock prescalers must be adjusted such that the SPI clock speed is limited to the following SPI clock rate: Master mode transmit 25-MHz MAX, master mode receive 12.5-MHz MAX

Slave mode transmit 12.5-MHz MAX, slave mode receive 12.5-MHz MAX.

(4)The active edge of the SPICLK signal referenced is controlled by the CLOCK POLARITY bit (SPICCR.6).

12

SPICLK (clock polarity = 0)

13

14

SPICLK (clock polarity = 1)

	17
	18
SPISOMI	SPISOMI Data Is Valid	Data Valid
	21
		22
SPISIMO	SPISIMO Data
	Must Be Valid

SPISTE(A)

A.In the slave mode, the SPISTE signal should be asserted low at least 0.5tc(SPC) before the valid SPI clock edge and remain low for at least 0.5tc(SPC) after the receiving edge (SPICLK) of the last data bit.

Figure 6-23. SPI Slave Mode External Timing (Clock Phase = 1)

124	Electrical Specifications	Copyright © 2003–2009, Texas Instruments Incorporated
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