Texas Instruments TMS320F2808, TMS320F2809 Gpiolmpsel GPIOXINT1SEL GPIOXINT2SEL, Gpioxnmisel

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009 www.ti.com

4.11 GPIO MUX

On the 280x, the GPIO MUX can multiplex up to three independent peripheral signals on a single GPIO pin in addition to providing individual pin bit-banging IO capability. The GPIO MUX block diagram per pin is shown in Figure 4-16. Because of the open drain capabilities of the I2C pins, the GPIO MUX block diagram for these pins differ. See the TMS320x280x, 2801x, 2804x DSP System Control and Interrupts Reference Guide (literature number SPRU712) for details.

GPIOx pin

	GPIOLMPSEL	GPIOXINT1SEL
		GPIOXINT2SEL
	LPMCR0
		GPIOXNMISEL
	Low Power	External Interrupt		PIE
	Modes Block	MUX
	Asynchronous			GPxDAT (read)
	path
	GPxQSEL1/2
	GPxCTRL		N/C
GPxPUD		00
	Input	01	Peripheral 1 Input
Internal
	Qualification		Peripheral 2 Input
Pullup		10
		11	Peripheral 3 Input
	Asynchronous path			GPxTOGGLE
				GPxCLEAR
				GPxSET

			00
					GPxDAT (latch)
			01		Peripheral 1 Output
			10		Peripheral 2 Output
High Impedance			11	Peripheral 3 Output
Output Control
			00		GPxDIR (latch)
	0 = Input, 1 = Output		01		Peripheral 1 Output Enable
			10		Peripheral 2 Output Enable
		XRS
			11		Peripheral 3 Output Enable

= Default at Reset

GPxMUX1/2

A.x stands for the port, either A or B. For example, GPxDIR refers to either the GPADIR and GPBDIR register depending on the particular GPIO pin selected.

B.GPxDAT latch/read are accessed at the same memory location.

Figure 4-16. GPIO MUX Block Diagram

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