Texas Instruments TMS320F2802, TMS320F2809, TMS320F2808, TMS320C2802, TMS320C2801 Xclkout, OSCCLK/8A

TMS320F2809, TMS320F2808, TMS320F2806

TMS320F2802, TMS320F2801, TMS320C2802

TMS320C2801, TMS320F28016, TMS320F28015

www.ti.com SPRS230L –OCTOBER 2003 –REVISED DECEMBER 2009

VDDIO, VDD3VFL

VDDA2, VDDAIO

(3.3 V)

VDD, VDD1A18,

VDD2A18

(1.8 V)

XCLKIN

X1/X2

XCLKOUT

tOSCST

OSCCLK/8(A)

User-Code Dependent

tw(RSL1)

XRS

Address/Data/ Control (Internal)

Boot-Mode Pins

Address/Data Valid. Internal Boot-ROM Code Execution Phase

td(EX)	User-Code Execution Phase
th(boot-mode)(B)	User-Code Dependent
GPIO Pins as Input

Boot-ROM Execution Starts

Peripheral/GPIO Function Based on Boot Code

I/O Pins(C)

GPIO Pins as Input (State Depends on Internal PU/PD)

User-Code Dependent

A.Upon power up, SYSCLKOUT is OSCCLK/2. Since the XCLKOUTDIV bits in the XCLK register come up with a reset state of 0, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This explains why XCLKOUT = OSCCLK/8 during this phase.

B.After reset, the boot ROM code samples Boot Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot code function. If boot ROM code executes after power-on conditions (in debugger environment), the boot code execution time is based on the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL enabled.

C.See Section 6.8 for requirements to ensure a high-impedance state for GPIO pins during power-up.

Figure 6-8. Power-on Reset

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TMS320C2801 TMS320F28016 TMS320F28015