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User Manual | November 21st, 2008 |
XTRNB: Attempting to allocate large buffer of size 1074503680
Logged during XTR initialization phase just before XTR tries to allocate memory to simulate DIMM.
XTRNB: Sending APIC initialization data to CPU0
Logged during XTR initialization phase just before APIC memory is initialized.
XTRNB: Write to TSC ignored. Please use M00000010 for writes to TSC
Logged during XTR initialization phase.
XTRNB: CPU0 rejected Initialization SREG XXXXXXXXXX with zeros
Logged during XTR initialization phase and displayed if the initialization data is invalid for the SREG. This may or may not be an error in the initialization data.
XTRNB: CPU0 rejected Initialization of SREG XXXXXXXXX with specific value
Logged during XTR initialization phase
XTRNB: Skipping write to μCode patch MSR C0010020
Logged during XTR initialization phase
XTRNB: Processing GETMEMPTR request for XXXXXXXXXXX:...Denied
Logged during XTR execution phase where XXXXXX is the physical address of page requested. The request may be denied if it is requested for a MMIO region.
**DEVMC_READMEM [800000007F1CAD00/296]: 55 8B EC 51 56 8B 75 0C
**DEVMC_WRITEMEM [400000007F294FD4/523]: A9 17 53 80
Logged during XTR execution phase. 800000007F1CAD00 is the address 296 is the instruction count. The data following the ":" is the data that returned and received to and from the CPU. This message is logged for a READ/WRITE MEMORY request but no record is present in XTR XML file for this read. The data is hence served and written from and to backing store (whose contents were originally initialized from the XTR binary file)
XTRNB: Ir A03E w/event time = 326, Consume time = 597, CPU ICount = 99: 01 00
XTRNB: Iw A03E w/event time = 345, Consume time = 616, CPU ICount = 118: 00 00
XTRNB: Ia D1 w/event time = 326462, Consume time = 326462, CPU ICount = 326235
Logged during XTR execution phase when IOR/IOW message is received by XTRNB. A03E is the address of IOR/IOW and the data after the ":" is the data that is returned and received to and from the CPU. „Ia‟ is for Interrupt Acknowledgement and D1 is the vector.
XTRNB: Time Resync - Adjusting time by
Logged during execution when there is a timing discrepancy detected between an event in XTR XML and that received from the CPU. XTRNB adjusts to this discrepancy. In ideal environment this should not occur.
XTRNB: Queuing event CPU0[DMAW] for time 8403
Logged during execution when a DMAW event is queued so that it could be triggered at a later point. 8403 is the time when this event should be triggered.
Chapter 7: Device Configuration | 113 |
