AMD 4.4.5 user manual Opcode Instruction Description

AMD Confidential

November 21st, 2008

User Manual

Instruction

Supported

Mnemonic

Opcode

Description

SGDT mem16:32

0F

01

/0

Store

global

descriptor

table

register

to

memory.

SGDT mem16:64

0F

01

/0

Store

global

descriptor

table

register

to

memory.

SIDT mem16:32

0F

01

/1

Store interrupt descriptor table register to

memory.

SIDT mem16:64

0F

01

/1

Store interrupt descriptor table register to

memory.

Store

the

segment

selector

from

the

local

SLDT reg16

0F

00

/0

descriptor

table

register

to

a

16-bit

register.

Store

the

segment

selector

from

the

local

SLDT reg32

0F

00

/0

descriptor

table

register

to

a

32-bit

register.

Store

the

segment

selector

from

the

local

SLDT reg64

0F

00

/0

descriptor

table

register

to

a

64-bit

register.

Store

the

segment

selector

from

the

local

SLDT mem16

0F

00

/0

descriptor table register to a 16-bit memory

location.

SMSW reg16

0F

01

/4

Store

the

low

16

bits

of

CR0

to

a

16-bit

register.

SMSW reg32

0F

01

/4

Store

the

low

32

bits

of

CR0

to

a

32-bit

register.

SMSW reg64

0F

01

/4

Store the entire 64 bits of CR0 to a 64-bit

register.

SMSW mem16

0F

01

/4

Store the low 16 bits of CR0 to memory.

STI

FB

Set interrupt flag (IF) to 1.

Store

the

segment

selector

from

the

task

STR reg16

0F

00

/1

register

to

a

16-bit

general-purpose

register.

Store

the

segment

selector

from

the

task

STR reg32

0F

00

/1

register

to

a

32-bit

general-purpose

register.

Store

the

segment

selector

from

the

task

STR reg64

0F

00

/1

register

to

a

64-bit

general-purpose

register.

STR mem16

0F

00

/1

Store

the

segment

selector

from

the

task

register to a 16-bit memory location.

SWAPGS

0F

01

F8

Exchange GS base with KernelGSBase MSR.

SYSCALL

0F

05

Call operating system.

SYSENTER

0F

34

Call operating system.

SYSEXIT

0F

35

Return from operating system.

SYSRET

0F

07

Return from operating system.

UD2

0F

08

Raise an invalid opcode exception.

VERR reg/mem16

0F

00

/4

Set the zero flag

(ZF)

to

1

if

the

segment

selected can be read.

VERW

0F

00

/5

Set the zero flag

(ZF)

to

1

if

the

segment

selected can be written.

Write modified cache lines to main memory,

WBINVD

0F

09

invalidate internal caches, and trigger

external cache flushes.

WRMSR

0F

30

Write EDX:EAX to the MSR specified by ECX.

Table 15-9: System Instruction Reference

A.6.3.1	INT – Interrupt to Vector
Opcode	Instruction		Description
CD	INT	imm8	Interrupt to Vector.
CC	INT	3	Interrupt to Debug Vector.

222 Appendix A