AMD Confidential

 

 

 

 

 

November 21st, 2008

User Manual

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Instruction

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Supported

 

 

Mnemonic

 

 

Opcode

 

 

 

 

 

 

 

Description

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Compare EDX:EAX register to 64-bit

 

 

 

 

 

 

 

 

memory location. If equal, set the

 

 

 

 

 

 

 

 

zero

flag

(ZF)

to

1

and

copy

the

 

CMPXCHG8B

 

 

0F C7 /1 m64

 

ECX:EBX

 

register

to

the

memory

 

 

 

 

 

 

 

 

location. Otherwise, copy the memory

 

 

 

 

 

 

 

 

location

to EDX:EAX and clear the

 

 

 

 

 

 

 

 

zero flag.

 

 

 

 

 

 

 

 

 

 

 

 

 

CPUID

 

 

0F A2

 

Executes

 

the

CPUID

function

whose

 

 

 

 

number is in the EAX register.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DAA

 

27

 

 

Decimal adjust AL.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DAS

 

 

2F

 

Decimal adjusts AL after subtraction.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEC reg/mem8

 

 

FE /1

 

Decrement

 

the

contents

of

an

8-bit

 

 

 

 

register or memory location by 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEC reg/mem16

 

 

FF /1

 

Decrement

 

the

contents

of

a

16-bit

 

 

 

 

register or memory location by 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEC reg/mem32

 

 

FF /1

 

Decrement

 

the

contents

of

a

32-bit

 

 

 

 

register or memory location by 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEC reg/mem64

 

 

FF /1

 

Decrement

 

the

contents

of

a

64-bit

 

 

 

 

register or memory location by 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEC reg16

 

 

48 +rw

 

Decrement

 

the

contents

of

a

16-bit

 

 

 

 

register by 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

DEC reg32

 

 

48 +rd

 

Decrement

 

the

contents

of

a

32-bit

 

 

 

 

register by 1.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Perform

unsigned

division

of

AX

 

by

 

 

 

 

 

 

 

 

the contents of an 8-bit register or

 

DIV reg/mem8

 

 

F6 /6

 

memory

 

location

 

and

store

 

the

 

 

 

 

 

 

 

 

quotient in AL and the remainder in

 

 

 

 

 

 

 

 

AH.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Perform unsigned division of DX:AX by

 

 

 

 

 

 

 

 

the contents of a 16-bit register or

 

DIV reg/mem16

 

 

F7 /6

 

memory

 

location

 

and

store

 

the

 

 

 

 

 

 

 

 

quotient in AX and the remainder in

 

 

 

 

 

 

 

 

DX.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Perform unsigned division of EDX:EAX

 

 

 

 

 

 

 

 

by the contents of a 32-bit register

 

DIV reg/mem32

 

 

F7 /6

 

or

memory

location

and

store

the

 

 

 

 

 

 

 

 

quotient in EAX and the remainder in

 

 

 

 

 

 

 

 

EDX.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Perform unsigned division of RDX:RAX

 

 

 

 

 

 

 

 

by the contents of a 64-bit register

 

DIV reg/mem64

 

 

F7 /6

 

or

memory

location

and

store

the

 

 

 

 

 

 

 

 

quotient in RAX and the remainder in

 

 

 

 

 

 

 

 

RDX.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENTER imm16,0

 

 

CB iw 00

 

Create a procedure stack frame.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENTER imm16,1

 

 

CB iw 01

 

Create

a

 

nested

stack

frame

for

a

 

 

 

 

procedure.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

ENTER imm16,imm8

 

 

CB iw ib

 

Create

a

 

nested

stack

frame

for

a

 

 

 

 

procedure.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Perform signed division of AX by the

 

 

 

 

 

 

 

 

contents

 

of an 8-bit register or

 

IDIV reg/mem8

 

 

F6 /7

 

memory

 

location

 

and

store

 

the

 

 

 

 

 

 

 

 

quotient in AL and the remainder in

 

 

 

 

 

 

 

 

AH.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Perform signed division of DX:AX by

 

 

 

 

 

 

 

 

the contents of a 16-bit register or

 

IDIV reg/mem16

 

 

F7 /7

 

memory

 

location

 

and

store

 

the

 

 

 

 

 

 

 

 

quotient in AX and the remainder in

 

 

 

 

 

 

 

 

DX.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

Perform signed division of EDX:EAX by

 

 

 

 

 

 

 

 

the contents of a 32-bit register or

 

IDIV reg/mem32

 

 

F7 /7

 

memory

 

location

 

and

store

 

the

 

 

 

 

 

 

 

 

quotient in EAX and the remainder in

 

 

 

 

 

 

 

 

EDX.

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

 

196

Appendix A

Page 208
Image 208
AMD 4.4.5 DEC reg/mem8, DEC reg/mem16, DEC reg/mem32, DEC reg/mem64, DEC reg16, DEC reg32, DIV reg/mem8, DIV reg/mem16

4.4.5 specifications

AMD 4.4.5 is a robust version of the AMD software ecosystem that focuses on enhanced performance, stability, and efficiency for users relying on AMD processors and graphics cards. This iteration brings various features and technologies designed to optimize gaming, professional applications, and general computing tasks.

One of the standout enhancements in AMD 4.4.5 is the integration of Smart Access Memory technology, which allows the CPU to access the full graphics memory directly. This feature enhances data flow between the CPU and GPU, leading to improved frame rates and overall performance, especially in memory-intensive games. Users can experience a marked increase in gaming performance without the need for additional hardware upgrades.

Another significant feature introduced is the updated Radeon Software Adrenalin Edition. This software update encompasses optimizations for various games, ensuring that gamers can enjoy a seamless experience with the latest titles. The Adrenalin interface also provides features such as Radeon Chill, which helps reduce power consumption during less demanding scenes, and Radeon Anti-Lag, designed to minimize input lag and enhance responsiveness in competitive gaming.

Additionally, AMD 4.4.5 brings the latest drivers that include important performance enhancements and bug fixes that allow for greater system stability. Regular updates ensure that users have the best experience with their AMD hardware, and it significantly bolsters compatibility with the latest gaming titles and software applications.

AMD's Enhanced Sync technology offers users the ability to eliminate screen tearing and stuttering while delivering smooth gameplay. It dynamically synchronizes the refresh rate of the display with the frame rates produced by the GPU, improving the visual experience significantly.

With the introduction of FidelityFX Super Resolution, AMD continues to bolster its suite of technologies that enhance graphics quality and performance. This feature allows lower-resolution images to be upscaled effectively, making it easier for users to enjoy high-end visuals without taxing their hardware excessively.

In summary, AMD 4.4.5 represents a comprehensive update for users by integrating cutting-edge technologies that cater to a wide range of applications from gaming to content creation. With enhancements across the board, AMD reaffirms its commitment to providing high-performance solutions that keep pace with the ever-evolving technology landscape. Whether for gaming aficionados or professional creators, the capabilities offered in this version make it a significant milestone in the AMD software ecosystem.