AMD 4.4.5 user manual AMD-8111 Southbridge Devices IO Hubs, Common Configuration Options

	AMD Confidential
User Manual	November 21st, 2008

7.11 AMD-8111™ Southbridge Devices – IO Hubs

The Southbridge devices provide the basic I/O Southbridge functionality of the system. Features include a PIO-mode IDE controller, register set for the USB controller(s), an LPC/ISA bridge, a system-management bus controller, IOAPIC bus bridge if applicable, and legacy AT devices (PIC, PIT, CMOS, timer, and DMA controller). The legacies AT devices have the standard behavior and IO addresses unless otherwise noted.

Interfaces

The Southbridge devices have several connection points. Possible connection points include a PCI bus, a SMB bus, a LPC bus, an INT/IOAPIC bus for interrupt signaling, and ISA and HyperTransport ports depending on the device type. The PCI bus acts as a host bus (AMD-8111). The SMB connects to devices such as the DIMM or the SMB hub. The LPC bus provides connectivity to devices such as Super IO's and BIOS ROMs. A HyperTransport port is used for main connectivity for the AMD-8111 device to the reset of the system.

Initialization and Reset State

When first initialized, the Southbridge devices are in the default state. This is described in detail in the respective datasheets. The legacy CMOS sub device initializes to all zeroes.

When reset, a Southbridge device takes on all default register values as above. The exception to this is that the CMOS contents remain the same.

Contents of a BSD

The BSD file contains the contents of all registers. It also saves the contents of any buffers, and states of all internal devices (HDD controllers, PIT, PIC, etc.). When the BSD file is read in, all buffers are filled with past data, and all states are restored to their saved states.

Common Configuration Options

The USB dialogue window, shown in Figure 7-20,gives the user the ability to enable or disable USB ports of the USB controller. USB devices which are connected to disabled USB ports won't be identified and detected by an operating system.

For instance, in Figure 7-20the USB Port 0 is disabled and USB Port 1 and 2 are enabled.

90 Chapter 7: Device Configuration