DIMM | DIMMs | DIMM Size | Operating Frequency (in MT/s) | Maximum DIMM Rank/ | |
Type | Populated/ |
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| Channel (DPC) |
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| DDR3 (1.5 V) | DDR3 (1.35 V) |
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| 2 | 32 GB / 64 GB | 1600 | 1333 | Quad rank physical |
| 3 | 32 GB / 64 GB | 1333 and 1066 | Not Applicable | Quad rank physical |
General Memory Module Installation Guidelines
Your system supports Flexible Memory Configuration, enabling the system to be configured and run in any valid chipset architectural configuration. The following are the recommended guidelines for best performance:
•RDIMMs and LRDIMMs must not be mixed.
•x4 and x8 DRAM based DIMMs can be mixed. For more information, see
•Populate only one
•Populate up to three dual- or
•Up to three quad rank LRDIMMs can be populated per channel.
•Up to three LRDIMMs can be populated regardless of rank count.
•Populate DIMM sockets only if a processor is installed. For
•Populate all sockets with white release lever first, then black, and then green.
•Populate the sockets by highest rank count in the following order — first in sockets with white release levers, then black, and then green. For example, if you want to mix
•The memory configuration for each processor should be identical. For example, if you populate socket A1 and B1 for processor 1, then populate socket C1 and D1 for processor 2, and so on.
•Memory modules of different sizes can be mixed provided that other memory population rules are followed (for example, 4 GB and 8 GB, and 16 GB memory modules can be mixed).
•Populate four DIMMs per processor (one DIMM per channel) at a time to maximize performance.
•If memory modules with different speeds are installed, they will operate at the speed of the slowest installed memory module(s) or slower depending on system DIMM configuration.
Mode-Specific Guidelines
Four memory channels are allocated to each processor. The allowable configurations depend on the memory mode selected.
NOTE: x4 and x8 DRAM based DIMMs can be mixed providing support for RAS features. However, all guidelines for specific RAS features must be followed. x4 DRAM based DIMMs retain Single Device Data Correction (SDDC) in memory optimized (independent channel) mode. x8 DRAM based DIMMs require Advanced ECC mode to gain SDDC.
The following sections provide additional slot population guidelines for each mode.
Advanced ECC (Lockstep)
Advanced ECC mode extends SDDC from x4 DRAM based DIMMs to both x4 and x8 DRAMs. This protects against single DRAM chip failures during normal operation.
Memory installation guidelines:
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