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Intel 440GX manual Debug Logic Recommendations, Debug Recommendations

Models: 440GX

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Debug Recommendations

Inputs to the Slot 1 connector, from system logic (assuming a 14mA driver):

•	PWRGOOD	150 - 330 ohm
•	INIT#	150 - 330 ohm
•	LINT[0]/INTR	150 - 330 ohm
•	LINT[1]/NMI	150 - 330 ohm
•	IGNNE#	150 - 330 ohm
•	A20M#	150 - 330 ohm

Bi-directional signal to/from the Slot 1 connector:

•	PICD[0]#	150 ohm
•	PICD[1]#	150 ohm

Inputs to the Slot 1 connector, only pull-up:

• FLUSH#

510 ohm

4.3.2Debug Logic Recommendations

Debug Recommendations are intended to assist in the development of the Intel® Pentium® II processor system and products utilizing it. The following are strongly recommended for early prototype designs only.

•Provide a push button reset circuit, do not rely on power-on reset from the power supply. A push-button reset usually results in more repeatable results when debugging initialization problems.

•Include a Intel® Pentium® II processor debug port connector. Intel cannot provide debug assistance without this connection. See the Integration tools chapter of the processor datasheet for schematics and a signal checklist. Be sure it is the proper 0.050” x .100” (1.27mm x 4mm) spacing connector.

•Provide the capability to measure the processor’s case temperature (Tplate) to ensure that the maximum temperature specification per processor Intel® Pentium® II Processor Datasheet.

•Place an SMA style (or similar) coaxial connector on the power plane between the VRM Header or on board voltage regulator and Slot 1 connector so that power plane noise can be monitored on systems. Note: an SMA to BNC cable for an oscilloscope may be needed as well. This component would only be placed during design evaluation.

•For DP systems, an empty Slot 1 connector is not allowed because one end of the bus termination would be missing.

•The ITP565 requires a complete boundary scan chain. For a DP system It is recommended that jumpers be placed on the motherboard to allow the boundary scan chain to bypass an “empty processor slot”.

•TRST# must be driven low during reset to all components with TRST# pins. Connecting a pull-down resistor to TRST# will accomplish the reset of the port.

Intel®440GX AGPset Design Guide

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Intel 440GX manual Debug Logic Recommendations, Debug Recommendations

Contents

March Design GuideIntel 440GX AGPset Intel440GX AGPset Design Guide Contents Validation 82371EB PIIX4E 4.3.1 IntelPentiumII Processor LAI Issue Figures Tables Revision History Intel440GX AGPset Design GuideDate RevisionIntel440GX AGPset Design Guide Introduction Page Introduction Introduction1.1 About This Design Guide 1.2 References Intel 440GX AGPset Datasheet WWW order numberIntroduction AP-589 EMI WWW order numberIntroduction 1.3 Intel Pentium II Processor / Intel 440GX AGPset Overview1.3.1 Intel Pentium II Processor 1.3.2 Intel 440GX AGPset Introduction1.3.2.1 System Bus Interface 1.3.2.2 DRAM Interface1.3.2.3 Accelerated Graphics Port Interface Introduction1.3.4 Wired for Management Initiative 1.3.3 PCI-to-ISA/IDE Xcelerator PIIX4E1.3.2.4 PCI Interface 1.3.2.5 System ClockingIntroduction 1.3.3.2 Remote Service Boot1.3.3.1 Instrumentation 1.3.3.4 Power Management 1.4 Design Recommendations1.4.1 Voltage Definitions 1.3.3.3 Remote Wake-Up1.4.2 General Design Recommendations 1.4.3 Transitioning from Intel 440BX AGPset to Intel 440GXAGPset Design IntroductionIntroduction Intel440GX AGPset Design GuideMotherboard Design Page Figure 2-1. Major Signal Sections 82443GX Top View Motherboard Layout and RoutingGuidelines 2.1 BGA Quadrant AssignmentMotherboard Layout and Routing Guidelines ATX Form FactorNLX Form Factor 2.2 Board DescriptionMotherboard Layout and Routing Guidelines Figure 2-4. Four Layer Board Stack-up Motherboard Layout and Routing Guidelines2.3 Routing Guidelines Motherboard Layout and Routing Guidelines2.3.1 GTL+ Description 2.3.2 GTL+ Layout Recommendations2.3.3 Single Processor Design 2.3.3.1 Single Processor Network Topology and ConditionsMotherboard Layout and Routing Guidelines 2.3.3.2 Single Processor Recommended Trace LengthsTable 2-1. Recommended Trace Lengths for Single Processor Design 2.3.4 Dual Processor Systems 2.3.5 Single Processor Systems-Single-End Termination SET2.3.4.1 Dual Processor Network Topology and Conditions 2.3.4.2 Dual Processor Recommended Trace LengthsMotherboard Layout and Routing Guidelines 2.3.5.2 SET Trace Length RequirementsTable 2-3. SET Trace Length Requirements 2.3.6 Additional Guidelines 2.3.6.1 Minimizing Crosstalk2.3.6.2 Practical Considerations Motherboard Layout and Routing Guidelines2.3.7 Design Methodology Motherboard Layout and Routing GuidelinesMotherboard Layout and Routing Guidelines 2.3.8 Performance RequirementsFigure 2-12. GTL+ Design Process 2.3.9 Topology Definition 2.3.10 Pre-Layout Simulation Sensitivity Analysis2.3.11 Simulation Methodology Table 2-4. Recommended 100 MHz System Flight Time Specs2.4 Placement & Layout 2.5 Post-Layout SimulationFigure 2-13. Pre-layout simulation process Motherboard Layout and Routing Guidelines2.5.1 Crosstalk and the Multi-Bit Adjustment Factor 2.6 Validation2.6.1 Flight Time Measurement Motherboard Layout and Routing Guidelines2.6.2 Signal Quality Measurement Motherboard Layout and Routing GuidelinesEdge Guideline @ Processor EdgeThe terms used in the equations are described in Table 2.7 Timing AnalysisMotherboard Layout and Routing Guidelines Table 2-10. Recommended 100 MHz System Timing Parameters Table 2-11. Recommended 100 MHz System Flight Time SpecsMotherboard Layout and Routing Guidelines Tflight,min2.8.1 AGP Connector “Up Option Layout Guidelines Figure 2-14. AGP Connector Layout Guidelines2.8 AGP Layout and Routing Guidelines Table 2-12. Data and Associated StrobeTable 2-14. Control Signal Line Length Recommendations 2.8.2 On-board AGP Compliant Device “Down” Option Layout GuidelinesTable 2-13. Source Synchronous Motherboard Recommendations Motherboard Layout and Routing GuidelinesTable 2-16. Control Signal Line Length Recommendations Figure 2-15. On-board AGP Compliant Device Layout GuidelinesTable 2-15. Source Synchronous Motherboard Recommendations Motherboard Layout and Routing GuidelinesFigure 2-16. FET Switch Example 2.9 82443GX Memory Subsystem Layout and Routing Guidelines2.9.1 100 MHz 82443GX Memory Array Considerations Motherboard Layout and Routing Guidelines2.9.1.1 Matching the Reference Planes 2.9.1.2 Adding Additional Decoupling CapacitorFigure 2-17. Registered SDRAM DIMM Example Table 2-17. MDx lines Reference Planes Routing2.9.2 Memory Layout & Routing Guidelines 2.9.1.3 Trace Width vs. Trace SpacingFigure 2-19. 4 DIMMs Single or Double-Sided Motherboard Layout and Routing GuidelinesTable 2-18. FET Switch DQ Route Example Figure 2-20. Motherboard Model-Data MDxx, 4 DIMMs82443GX Motherboard Layout and Routing GuidelinesFigure 2-21. Motherboard Model-DQMA0,24,67, 4 DIMMs Figure 2-22. Motherboard Model-DQMA1,5, 4 DIMMsFigure 2-23. Motherboard Model-DQMA1,5, 4 DIMMs Motherboard Layout and Routing GuidelinesFigure 2-24. Motherboard Model-DQMB1,5, 4 DIMMs Figure 2-25. Motherboard Model-CSA#/CSB#, 4 DIMMsFigure 2-26. Motherboard Model-SRASA#, 4 DIMMs Motherboard Layout and Routing GuidelinesTable 2-19. Motherboard Model SRASB#, 4 DIMMs Table 2-20. Motherboard Model SCASA#, 4 DIMMsTable 2-21. Motherboard Model SCASB#, 4 DIMMs Motherboard Layout and Routing GuidelinesTable 2-22. Motherboard Model WEA#, 4 DIMMs Table 2-23. Motherboard Model WEB#, 4 DIMMsTable 2-24. Motherboard Model MAA140, 4 DIMMs Motherboard Layout and Routing Guidelines2.9.3 4 DIMM Routing Guidelines NO FET 2.9.4 PCI Bus Routing GuidelinesTable 2-25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs Figure 2-27. Motherboard Model-Data MDxx Lines, 4 DIMMs No FET2.9.5 Decoupling Guidelines Intel 440GX AGPset Platform Host Bridge Controller 492 BGAFigure 2-28. PCI Bus Layout Example Figure 2-29. 82443GX Decoupling2.9.6 Intel 440GX AGPset Clock Layout Recommendations 2.9.6.1 Clock Routing Spacing2.9.6.2 System Bus Clock Layout Figure 2-30. Clock Trace Spacing GuidelinesMotherboard Layout and Routing Guidelines 2.9.6.3 PCI Clock Layout2.9.6.4 SDRAM Clock Layout Motherboard Layout and Routing Guidelines 2.9.6.5 AGP Clock LayoutFigure 2-31. AGP Clock Layout Design Checklist Page Design Checklist Design Checklist3.1 Overview 3.2 Pull-up and Pull-down Resistor Values3.3 Intel Pentium II Processor Checklist 3.3.1 Intel Pentium II ProcessorFigure 3-1. Pull-up Resistor Example Table 3-1. Slot Connectivity Sheet 1 ofIntel440GX AGPset Design Guide Table 3-1. Slot Connectivity Sheet 2 ofDesign Checklist Table 3-2. GND & Power Pin Definition Table 3-1. Slot Connectivity Sheet 3 ofDesign Checklist Intel440GX AGPset Design GuideDesign Checklist 3.3.3 Intel Pentium II Processor Signals3.3.2 Intel Pentium II Processor Clocks Design Checklist DBRESET ITP Reset signal requires a 240 ohm pull-up to VCC33.3.4 Uni-Processor UP Slot 1 Checklist 3.3.5 Dual-Processor DP Slot 1 Checklist3.3.6 Slot 1 Decoupling Capacitors 3.3.7 Voltage Regulator Module, VRM3.4 Intel 440GX AGPset Clocks 3.4.1 CK100 - 100 MHz Clock SynthesizerTable 3-3. Processor Frequency Select Design Checklist3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer 3.4.3 GCKE and DCLKWR ConnectionFigure 3-2. GCKE & DCLKWR Connections Design Checklist3.5 82443GX Host Bridge 3.5.1 82443GX InterfaceTable 3-4. 82443GX Connectivity Sheet 1 of Design ChecklistTable 3-4. 82443GX Connectivity Sheet 2 of Design ChecklistIntel440GX AGPset Design Guide 3-113.5.2 82443GX GTL+ Bus Interface 3.5.3 82443GX PCI InterfaceTable 3-4. 82443GX Connectivity Sheet 3 of Design ChecklistDesign Checklist 3.5.4 82443GX AGP InterfaceTable 3-5. Strapping Options 3.6 Intel 440GX AGPset Memory Interface 3.6.1 SDRAM ConnectionsTable 3-6. SDRAM Connectivity Design Checklist3.6.2 DIMM Solution With FET Switches Figure 3-3. Current Solution With Existing FET Switches3.6.3 Registered SDRAM Design Checklist3.7 82371EB PIIX4E 3.7.1 PIIX4E ConnectionsTable 3-7. PIIX4E Connectivity Sheet 1 of Design ChecklistTable 3-7. PIIX4E Connectivity Sheet 2 of Design ChecklistIntel440GX AGPset Design Guide 3-17Table 3-7. PIIX4E Connectivity Sheet 3 of Design ChecklistIntel440GX AGPset Design Guide 3-18Table 3-7. PIIX4E Connectivity Sheet 4 of Design ChecklistIntel440GX AGPset Design Guide 3-193.7.2 IDE Routing Guidelines 3.7.2.1 Cabling3.7.2.2 Motherboard Table 3-8. IDE Series TerminationDesign Checklist Figure 3-4. Series Resistor Placement for Primary IDE ConnectorsPIIX4E 3.8 PCI Bus Signals 3.7.3 PIIX4E Power And Ground PinsTable 3-9. PIIX4E PWR & GND Design ChecklistISA Signals 3.10 ISA and X-Bus SignalsTable 3-10. Non-PIIX4E PCI Signals Table 3-11. Non-PIIX4E ISA Signals3.11 USB Interface 3.12 IDE InterfaceTable 3-12. Non-PIIX4E IDE Design Checklist3.13 Flash Design 3.13.1 Dual-Footprint Flash Design3.13.2 Flash Design Considerations Figure 3-5. Dual Footprint Flash LayoutsXD70 1Mbit/2MbitFlash Figure 3-6. nterfacing Intel’s Flash with PIIX4E in DesktopWrite Protection Table 3-13. Flash Vpp RecommendationsDesign Checklist 3.14 System and Test Signals 3.15 Power Management SignalsFigure 3-7. Interfacing Intel’s Flash with PIIX4E in Desktop Design ChecklistSimplified P W R G O O D a n d P W R O K generation logic VCC3 A S L O T O C C B S L O T O C C4.7K V R M 1 P W R G DV R M 2 P W R G D I T P R E S E T A T X P S P O K Note The polarities have been altered to simplify drawing3.15.1 Power Button Implementation Design Checklist3.16 Miscellaneous Design Checklist3.17 82093AA IOAPIC Design Checklist3.18.1 Max1617 Temperature Sensor 3.18 Manageability Devices3.18.2 LM79 Microprocessor System Hardware Monitor Design Checklist3.18.3 82558B LOM Checklist Design Checklist3.19 Software/BIOS 3.19.1 USB and Multi-processor BIOS3.18.4 Wake On LAN WOL Header Design Checklist3.20 Thermals / Cooling Solutions 3.21 Mechanicals3.19.2 Design Considerations 3.20.1 Design Considerations3.22 Electricals 3.21.1 Design Considerations3.22.1 Design Considerations Design Checklist3.23 Layout Checklist 3.24 Applications and Add-in Hardware3.23.1 Routing and Board Fabrication 3.23.2 Design ConsiderationDebug Recommendations Page Debug Recommendations 4.1 Slot 1 Test Tools4.2 Debug/Simulation Tools 4.2.1 Logic Analyzer Interface LAI4.3 Debug Features 4.3.1 Intel Pentium II Processor LAI Issue4.2.3 Bus Functional Model BFM 4.2.4 I/O Buffer ModelsFigure 4-1. LAI Probe Input Circuit Debug Recommendations4.3.2 Debug Logic Recommendations Debug Recommendations4.3.4 Debug Procedures 4.3.3 Debug Layout4.3.2.1 Debug Considerations 4.3.3.1 Design ConsiderationsDebug Recommendations DM = 0, D3-D0 = 1111 all including self shorthandThird Party Vendors Page Table 5-1. Slot 1 Connector Third-Party Vendor InformationProcessors Third-Party Vendor Information5.1.1 Voltage Regulator Modules 5.1.2 Voltage Regulator Control SiliconTable 5-4. Voltage Regulator Modules Table 5-5. Voltage Regulator Control Silicon Vendors5.2.2 Power Management Components 5.2.3 FET Switches4 DIMM/FET DesignTable 5-7. Power Management Component Vendors Table 5-8. FET Switch Vendors5.3.1 Slot 1 Connector 5.3 Other Processor Components5.3.2 Mechanical Support 5.3.3 Heat sinksReference Design Schematics Page Intel 440GX AGPset Platform Reference DesignIntel440GX AGPset Platform Reference Design 4 andIntel440GX AGPset Platform Reference Design The GCKE shift register circuit is also shownIntel440GX AGPset Platform Reference Design Ultra I/O ComponentPower Connectors Front Panel Jumpers Intel440GX AGPset Platform Reference DesignPull-up and Pull-down Resistors 34-35