Intel 440GX manual Placement & Layout, Post-Layout Simulation, 13. Pre-layout simulation process

Motherboard Layout and Routing Guidelines

The methodology that Intel recommends is known as “Sensitivity Analysis”. In sensitivity analysis, interconnect parameters are varied to understand how they affect system timing and signal integrity. Sensitivity analysis can be further broken into two types of analysis, parametric sweeps and Monte Carlo analysis, which are described below.

Figure 2-13. Pre-layout simulation process

Interconnect Simulations (Transmission-Line)

		Sensitivity Analyses
Performance as function of Length				Monte Carlo
	(flight time, signal quality, etc.)		(pass/fail as function of length)
				D U A L K L A M A T H P R O C E S S O R C A R D S O L U T IO N S P A C E
				M o n t e C a rl o

Solution Space

S o l u t io n s p a c e

2.4Placement & Layout

Once the pre-layout simulation is completed, route the board using the solution space resulting from the sensitivity analysis.

2.5Post-Layout Simulation

Following layout, extract the traces and run simulations to verify that the layout meets timing and noise requirements. A small amount of trace “tuning” may be required, but experience at Intel has shown that sensitivity analysis dramatically reduces the amount of tuning required.

The post layout simulations should take into account the expected variation for all interconnect parameters. For timing simulations, use a VREF of 2/3 VTT ± 2% for both the Intel® Pentium® II processor and Intel® 440GX AGPset components. Flight times measured from the Pentium II processor edge fingers to other system components use the standard flight time method.

2-14 Intel®440GX AGPset Design Guide