Design Checklist

•The system reset button has typically been connected indirectly to the PWROK input of the PIIX4/PIIX4E. This technique will not reset the suspend well logic, which includes the SMBus Host and Slave controllers. To reset the hardware in the suspend well, the reset button should be connected to the RSMRST# input of the PIIX4/PIIX4E. Assertion of RSMRST#, via a reset button, will result in a complete system reset. RSMRST# assertion will cause SUS[A-C]# to assert which results in the deassertion of PWROK if SUS[A:C]# controls the power supply PS-ON control signal. The deassertion of PWROK will cause the PIIX4/PIIX4E to assert PCIRST#, RSTDRV, and CPURST.

•In the reference schematics, 3VSB is generated from 5VSB on the power supply connector. The Zener diode, MMBZ5226BL, acts as a voltage regulator which clamps the standby voltage at 3.3V. The 0.1uF and 10uF caps are for noise decoupling and the 56 ohm series resistor is used for current limiting. This Zener diode and 56 ohm resistor should be validated to make sure the standby voltage is clamped to 3.3V. The series resistor may need to be tuned based on the standby current requirements of the board. As the 3VSB is required to supply more current, the voltage will drop slightly. Also note that the Zener being used requires approximately 20mA to sustain 3.3V, however a different Zener diode requiring less current may be used. Refer to the schematics for implementation details.

•RI# can be connected to the modem if this feature is used. To implement ring indicate as a wake event, the source driving the RI# signal must be powered when the PIIX4E suspend well is powered.

•SUSC# is connected to PS-ON (pin 14) of the power supply connector through an inverter to control the remote-off function.

•PCIREQ[3:0]# is connected between the PIIX4E and the PCI bus. Bus master request are considered as power management events.

•Connect SMBCLK and SMBDATA to 2.7K ohm (approximate) pull-up resistors to VCC3, and route to all DIMM sockets, PIIX4E, CKBF, LM79, LM75, and MAX1617. The 2.7K pull-up may not be sufficient for all these loads and their associated trace lengths. This needs to be considered on a design by design basis.

•SMBALERT# is pulled up to 3VSB with an 8.2K ohm (approximate) resistor.

3.15.1Power Button Implementation

The items below should be considered when implementing a power management model for a desktop system. The power states are as follows:

S1 - POS (Power On Suspend - CPU context not lost)

S2 - POSCCL (Power On Suspend CPU Context Lost)

S3 - STR (Suspend To RAM)

S4 - STD (Suspend To Disk)

S5 - Soft-off

•Wake: Pressing the power button wakes the computer from S1-S5.

•Sleep: Pressing the power button signals software/firmware in the following manner:

•If SCI is enabled, the power button will generate an SCI to the OS.

•The OS will implement the power button policy to allow orderly shutdowns.

•Do not override this with additional hardware.

•If SCI is not enabled:

•Enable the power button to generate an SMI and go directly to soft-off or a supported sleep state.

Intel®440GX AGPset Design Guide

3-30

Page 89 Page 91
Page 90
Image 90
Intel 440GX manual Power Button Implementation
Page 89 Page 91

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.
Top Page Image Contents