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Intel 440GX Debug Features, Bus Functional Model BFM, 4.2.4 I/O Buffer Models, FLOTHERM* Model

Models: 440GX

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Debug Recommendations

Contact your local Intel Field Sales representative to complete the proper software license agreement and non-disclosure agreement required to receive the ITP.

4.2.3Bus Functional Model (BFM)

A bus functional model for the Intel® Pentium® II processor system bus is available from third party vendors and requires a special non-disclosure agreement. Contact your local Intel Field Sales representative for information on the bus functional model vendors and to complete the appropriate non-disclosure agreements.

4.2.4I/O Buffer Models

IBIS Models are available from Intel for:

•Intel® Pentium® II processor (QUAD only, IBIS models TBD)

•82443GX IBIS Models

•PIIX4E PCI ISA IDE Xcelerator IBIS Models

Contact your local Intel Field Sales representative for a copy of these models and to complete the appropriate non-disclosure agreements.

4.2.5FLOTHERM* Model

A FLOTHERM* Model is available for the Intel® Pentium® II processor.

4.3Debug Features

These suggestions are for debug purposes only on initial prototype systems, and are not required for production level systems. Some of these features may be desirable test functions that you may incorporate onto production boards.

4.3.1Intel® Pentium® II Processor LAI Issue

Note: If the LAI562 tool is not being used, this issue can be ignored. However, be aware that if you send a system to Intel for debug, the absence of the required workarounds will prohibit debugassistance from Intel.

To maintain backward compatibility with Intel® Pentium® II processor, Intel suggests the following circuitry to be considered. The LAI562 integration tool has been designed such that an extra load will be presented on the CMOS signals connected to the Slot 1 connector. The following list of signals are affected:

PREQ#, TCK, TDI, TDO, TMS, TRST#, INIT#, FLUSH#, STPCLK#, PICCLK, PICD[1:0]#, LINT[0]/INTR, LINT[1]/NMI, IERR#, SMI#, PWRGOOD, THERMTRIP#, SLP#, FERR#, IGNNE# and A20M#.

Figure 4-1describes the CMOS probe signals of the LAI562.

Intel®440GX AGPset Design Guide

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Intel 440GX Debug Features, Bus Functional Model BFM, 4.2.4 I/O Buffer Models, FLOTHERM* Model, Debug Recommendations

Contents

Design Guide Intel 440GX AGPsetMarch Intel440GX AGPset Design Guide Contents Validation 82371EB PIIX4E 4.3.1 IntelPentiumII Processor LAI Issue Figures Tables Date Revision HistoryIntel440GX AGPset Design Guide RevisionIntel440GX AGPset Design Guide Introduction Page Introduction 1.1 About This Design GuideIntroduction Introduction 1.2 ReferencesIntel 440GX AGPset Datasheet WWW order number AP-589 EMI WWW order number1.3 Intel Pentium II Processor / Intel 440GX AGPset Overview 1.3.1 Intel Pentium II ProcessorIntroduction 1.3.2 Intel 440GX AGPset Introduction1.3.2.3 Accelerated Graphics Port Interface 1.3.2.1 System Bus Interface1.3.2.2 DRAM Interface Introduction1.3.2.4 PCI Interface 1.3.4 Wired for Management Initiative1.3.3 PCI-to-ISA/IDE Xcelerator PIIX4E 1.3.2.5 System Clocking1.3.3.2 Remote Service Boot 1.3.3.1 InstrumentationIntroduction 1.4.1 Voltage Definitions 1.3.3.4 Power Management1.4 Design Recommendations 1.3.3.3 Remote Wake-UpAGPset Design 1.4.2 General Design Recommendations1.4.3 Transitioning from Intel 440BX AGPset to Intel 440GX IntroductionIntroduction Intel440GX AGPset Design GuideMotherboard Design Page Guidelines Figure 2-1. Major Signal Sections 82443GX Top ViewMotherboard Layout and Routing 2.1 BGA Quadrant AssignmentMotherboard Layout and Routing Guidelines ATX Form Factor2.2 Board Description Motherboard Layout and Routing GuidelinesNLX Form Factor Figure 2-4. Four Layer Board Stack-up Motherboard Layout and Routing Guidelines2.3 Routing Guidelines Motherboard Layout and Routing Guidelines2.3.3 Single Processor Design 2.3.1 GTL+ Description2.3.2 GTL+ Layout Recommendations 2.3.3.1 Single Processor Network Topology and Conditions2.3.3.2 Single Processor Recommended Trace Lengths Table 2-1. Recommended Trace Lengths for Single Processor DesignMotherboard Layout and Routing Guidelines 2.3.4.1 Dual Processor Network Topology and Conditions 2.3.4 Dual Processor Systems2.3.5 Single Processor Systems-Single-End Termination SET 2.3.4.2 Dual Processor Recommended Trace Lengths2.3.5.2 SET Trace Length Requirements Table 2-3. SET Trace Length RequirementsMotherboard Layout and Routing Guidelines 2.3.6.2 Practical Considerations 2.3.6 Additional Guidelines2.3.6.1 Minimizing Crosstalk Motherboard Layout and Routing Guidelines2.3.7 Design Methodology Motherboard Layout and Routing Guidelines2.3.8 Performance Requirements Figure 2-12. GTL+ Design ProcessMotherboard Layout and Routing Guidelines 2.3.11 Simulation Methodology 2.3.9 Topology Definition2.3.10 Pre-Layout Simulation Sensitivity Analysis Table 2-4. Recommended 100 MHz System Flight Time SpecsFigure 2-13. Pre-layout simulation process 2.4 Placement & Layout2.5 Post-Layout Simulation Motherboard Layout and Routing Guidelines2.6.1 Flight Time Measurement 2.5.1 Crosstalk and the Multi-Bit Adjustment Factor2.6 Validation Motherboard Layout and Routing GuidelinesEdge 2.6.2 Signal Quality MeasurementMotherboard Layout and Routing Guidelines Guideline @ Processor Edge2.7 Timing Analysis Motherboard Layout and Routing GuidelinesThe terms used in the equations are described in Table Motherboard Layout and Routing Guidelines Table 2-10. Recommended 100 MHz System Timing ParametersTable 2-11. Recommended 100 MHz System Flight Time Specs Tflight,min2.8 AGP Layout and Routing Guidelines 2.8.1 AGP Connector “Up Option Layout GuidelinesFigure 2-14. AGP Connector Layout Guidelines Table 2-12. Data and Associated StrobeTable 2-13. Source Synchronous Motherboard Recommendations Table 2-14. Control Signal Line Length Recommendations2.8.2 On-board AGP Compliant Device “Down” Option Layout Guidelines Motherboard Layout and Routing GuidelinesTable 2-15. Source Synchronous Motherboard Recommendations Table 2-16. Control Signal Line Length RecommendationsFigure 2-15. On-board AGP Compliant Device Layout Guidelines Motherboard Layout and Routing Guidelines2.9.1 100 MHz 82443GX Memory Array Considerations Figure 2-16. FET Switch Example2.9 82443GX Memory Subsystem Layout and Routing Guidelines Motherboard Layout and Routing GuidelinesFigure 2-17. Registered SDRAM DIMM Example 2.9.1.1 Matching the Reference Planes2.9.1.2 Adding Additional Decoupling Capacitor Table 2-17. MDx lines Reference Planes RoutingFigure 2-19. 4 DIMMs Single or Double-Sided 2.9.2 Memory Layout & Routing Guidelines2.9.1.3 Trace Width vs. Trace Spacing Motherboard Layout and Routing Guidelines82443GX Table 2-18. FET Switch DQ Route ExampleFigure 2-20. Motherboard Model-Data MDxx, 4 DIMMs Motherboard Layout and Routing GuidelinesFigure 2-23. Motherboard Model-DQMA1,5, 4 DIMMs Figure 2-21. Motherboard Model-DQMA0,24,67, 4 DIMMsFigure 2-22. Motherboard Model-DQMA1,5, 4 DIMMs Motherboard Layout and Routing GuidelinesFigure 2-26. Motherboard Model-SRASA#, 4 DIMMs Figure 2-24. Motherboard Model-DQMB1,5, 4 DIMMsFigure 2-25. Motherboard Model-CSA#/CSB#, 4 DIMMs Motherboard Layout and Routing GuidelinesTable 2-21. Motherboard Model SCASB#, 4 DIMMs Table 2-19. Motherboard Model SRASB#, 4 DIMMsTable 2-20. Motherboard Model SCASA#, 4 DIMMs Motherboard Layout and Routing GuidelinesTable 2-24. Motherboard Model MAA140, 4 DIMMs Table 2-22. Motherboard Model WEA#, 4 DIMMsTable 2-23. Motherboard Model WEB#, 4 DIMMs Motherboard Layout and Routing GuidelinesTable 2-25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs 2.9.3 4 DIMM Routing Guidelines NO FET2.9.4 PCI Bus Routing Guidelines Figure 2-27. Motherboard Model-Data MDxx Lines, 4 DIMMs No FETFigure 2-28. PCI Bus Layout Example 2.9.5 Decoupling Guidelines Intel 440GX AGPset PlatformHost Bridge Controller 492 BGA Figure 2-29. 82443GX Decoupling2.9.6.2 System Bus Clock Layout 2.9.6 Intel 440GX AGPset Clock Layout Recommendations2.9.6.1 Clock Routing Spacing Figure 2-30. Clock Trace Spacing Guidelines2.9.6.3 PCI Clock Layout 2.9.6.4 SDRAM Clock LayoutMotherboard Layout and Routing Guidelines 2.9.6.5 AGP Clock Layout Figure 2-31. AGP Clock LayoutMotherboard Layout and Routing Guidelines Design Checklist Page 3.1 Overview Design ChecklistDesign Checklist 3.2 Pull-up and Pull-down Resistor ValuesFigure 3-1. Pull-up Resistor Example 3.3 Intel Pentium II Processor Checklist3.3.1 Intel Pentium II Processor Table 3-1. Slot Connectivity Sheet 1 ofTable 3-1. Slot Connectivity Sheet 2 of Design ChecklistIntel440GX AGPset Design Guide Design Checklist Table 3-2. GND & Power Pin DefinitionTable 3-1. Slot Connectivity Sheet 3 of Intel440GX AGPset Design Guide3.3.3 Intel Pentium II Processor Signals 3.3.2 Intel Pentium II Processor ClocksDesign Checklist Design Checklist DBRESET ITP Reset signal requires a 240 ohm pull-up to VCC33.3.6 Slot 1 Decoupling Capacitors 3.3.4 Uni-Processor UP Slot 1 Checklist3.3.5 Dual-Processor DP Slot 1 Checklist 3.3.7 Voltage Regulator Module, VRMTable 3-3. Processor Frequency Select 3.4 Intel 440GX AGPset Clocks3.4.1 CK100 - 100 MHz Clock Synthesizer Design ChecklistFigure 3-2. GCKE & DCLKWR Connections 3.4.2 CKBF - SDRAM 1 to 18 Clock Buffer3.4.3 GCKE and DCLKWR Connection Design ChecklistTable 3-4. 82443GX Connectivity Sheet 1 of 3.5 82443GX Host Bridge3.5.1 82443GX Interface Design ChecklistIntel440GX AGPset Design Guide Table 3-4. 82443GX Connectivity Sheet 2 ofDesign Checklist 3-11Table 3-4. 82443GX Connectivity Sheet 3 of 3.5.2 82443GX GTL+ Bus Interface3.5.3 82443GX PCI Interface Design Checklist3.5.4 82443GX AGP Interface Table 3-5. Strapping OptionsDesign Checklist Table 3-6. SDRAM Connectivity 3.6 Intel 440GX AGPset Memory Interface3.6.1 SDRAM Connections Design Checklist3.6.3 Registered SDRAM 3.6.2 DIMM Solution With FET SwitchesFigure 3-3. Current Solution With Existing FET Switches Design ChecklistTable 3-7. PIIX4E Connectivity Sheet 1 of 3.7 82371EB PIIX4E3.7.1 PIIX4E Connections Design ChecklistIntel440GX AGPset Design Guide Table 3-7. PIIX4E Connectivity Sheet 2 ofDesign Checklist 3-17Intel440GX AGPset Design Guide Table 3-7. PIIX4E Connectivity Sheet 3 ofDesign Checklist 3-18Intel440GX AGPset Design Guide Table 3-7. PIIX4E Connectivity Sheet 4 ofDesign Checklist 3-193.7.2.2 Motherboard 3.7.2 IDE Routing Guidelines3.7.2.1 Cabling Table 3-8. IDE Series TerminationFigure 3-4. Series Resistor Placement for Primary IDE Connectors PIIX4EDesign Checklist Table 3-9. PIIX4E PWR & GND 3.8 PCI Bus Signals3.7.3 PIIX4E Power And Ground Pins Design ChecklistTable 3-10. Non-PIIX4E PCI Signals ISA Signals3.10 ISA and X-Bus Signals Table 3-11. Non-PIIX4E ISA SignalsTable 3-12. Non-PIIX4E IDE 3.11 USB Interface3.12 IDE Interface Design Checklist3.13.2 Flash Design Considerations 3.13 Flash Design3.13.1 Dual-Footprint Flash Design Figure 3-5. Dual Footprint Flash LayoutsFlash XD701Mbit/2Mbit Figure 3-6. nterfacing Intel’s Flash with PIIX4E in DesktopTable 3-13. Flash Vpp Recommendations Design ChecklistWrite Protection Figure 3-7. Interfacing Intel’s Flash with PIIX4E in Desktop 3.14 System and Test Signals3.15 Power Management Signals Design ChecklistV R M 2 P W R G D I T P R E S E T A T X P S P O K Simplified P W R G O O D a n d P W R O K generation logic VCC3A S L O T O C C B S L O T O C C4.7K V R M 1 P W R G D Note The polarities have been altered to simplify drawing3.15.1 Power Button Implementation Design Checklist3.16 Miscellaneous Design Checklist3.17 82093AA IOAPIC Design Checklist3.18.2 LM79 Microprocessor System Hardware Monitor 3.18.1 Max1617 Temperature Sensor3.18 Manageability Devices Design Checklist3.18.3 82558B LOM Checklist Design Checklist3.18.4 Wake On LAN WOL Header 3.19 Software/BIOS3.19.1 USB and Multi-processor BIOS Design Checklist3.19.2 Design Considerations 3.20 Thermals / Cooling Solutions3.21 Mechanicals 3.20.1 Design Considerations3.22.1 Design Considerations 3.22 Electricals3.21.1 Design Considerations Design Checklist3.23.1 Routing and Board Fabrication 3.23 Layout Checklist3.24 Applications and Add-in Hardware 3.23.2 Design ConsiderationDebug Recommendations Page 4.2 Debug/Simulation Tools Debug Recommendations4.1 Slot 1 Test Tools 4.2.1 Logic Analyzer Interface LAI4.2.3 Bus Functional Model BFM 4.3 Debug Features4.3.1 Intel Pentium II Processor LAI Issue 4.2.4 I/O Buffer ModelsFigure 4-1. LAI Probe Input Circuit Debug Recommendations4.3.2 Debug Logic Recommendations Debug Recommendations4.3.2.1 Debug Considerations 4.3.4 Debug Procedures4.3.3 Debug Layout 4.3.3.1 Design ConsiderationsDebug Recommendations DM = 0, D3-D0 = 1111 all including self shorthandThird Party Vendors Page Processors Table 5-1. Slot 1 ConnectorThird-Party Vendor Information Third-Party Vendor InformationTable 5-4. Voltage Regulator Modules 5.1.1 Voltage Regulator Modules5.1.2 Voltage Regulator Control Silicon Table 5-5. Voltage Regulator Control Silicon VendorsTable 5-7. Power Management Component Vendors 5.2.2 Power Management Components5.2.3 FET Switches4 DIMM/FET Design Table 5-8. FET Switch Vendors5.3.2 Mechanical Support 5.3.1 Slot 1 Connector5.3 Other Processor Components 5.3.3 Heat sinksReference Design Schematics Page Intel440GX AGPset Platform Reference Design Intel 440GX AGPset Platform ReferenceDesign 4 andIntel440GX AGPset Platform Reference Design The GCKE shift register circuit is also shownIntel440GX AGPset Platform Reference Design Ultra I/O ComponentPull-up and Pull-down Resistors Power Connectors Front Panel JumpersIntel440GX AGPset Platform Reference Design 34-35