Intel Intel 440GX AGPset Clocks, 3.4.1 CK100 - 100 MHz Clock Synthesizer, Design Checklist

Design Checklist

3.4Intel® 440GX AGPset Clocks

3.4.1CK100 - 100 MHz Clock Synthesizer

•The system clock which provides 100 MHz to the processor and the Intel® 440GX AGPset, and the clocks for the APIC must be +2.5V.

•If implemented in the clock chip, pin 28, when strapped low, provides a spread spectrum modulation effect which may help reduce EMI. The modulation will be “down spread” only, meaning that the nominal 100/66 MHz frequencies will be modulated 0.25% to 0.5% below 100/66. While this may help EMI testing, performance will be impacted. Check with your clock vendor for availability of this feature.

•SEL pins on CK100 can be used to select special functionality using 8.2K ohm pull-ups to V

Table 3-3. Processor Frequency Select

SEL100/66#	SEL1	SEL0	Function
0	0	0	Tri-state
1	0	0	Test Mode
0	1	1	Active 66MHz
1	1	1	Active 100MHz

•Unused clocks should be terminated to ground with 22 ohm resistors.

•22 ohm series resistors are recommended on the CPU, PCI, and IOAPIC clock outputs.

•In a UP system, clock skew between the 82443GX and the CPU can be reduced by tying the clock driver pins together at the clock chip and driving the CPU and 82443GX from this net with a 10 Ohm resistor at the driver for each.

•10K ohm pull-ups to VCC3.3 are recommended on PCI_STP#, CPU_STP#, PWRDWN#. If POS is not supported, connecting these signals to the PIIX4E is not required. On reset, SUSA# (connected to PWRDWN#) is asserted, which causes the clock outputs to stop. This may cause problems with the ITP when connected. Zero ohm stuffing options can be used to select the functionality.

•Check with your clock vendor and the reference schematics for special layout and decoupling considerations. The reference schematics implement an LC filter on the supply pins to reduce noise.

Intel®440GX AGPset Design Guide 3-8