Intel 440GX manual Signal Quality Measurement, Motherboard Layout and Routing Guidelines, Edge

Motherboard Layout and Routing Guidelines

Table 2-5. System Timing Requirements for Validating Setup/Hold Windows

Driver	Receiver					Equation
Pentium®II	AGPset	Tmeasured	≥ Thold	+ Tskew,CLK		+ Tskew,PCB + Tclk ,max
processor
		Tmeasured	≤ Tcycle	− Tsu	− Tskew,CLK − Tskew,PCB − Tjit		− Tadj	+ Tclk,min
AGPset	Pentium®II	Tmeasured	≥ Thold + Tskew,CLK			+ Tskew,PCB − Tclk ,min
	processor
		Tmeasured	≤ Tcycle	− Tsu	− Tskew,CLK − Tskew,PCB − Tjit		− Tadj	− Tclk ,max
Pentium®II	Pentium®II	Tmeasured	≥ Thold + Tskew,CLK			+ Tskew,PCB
processor	processor
		Tmeasured	≤ Tcycle	− Tsu	− Tskew,CLK − Tskew,PCB − Tjit		− Tadj

2.6.2Signal Quality Measurement

Signal integrity is specified at the processor core, which is not accessible. Intel has found that there can be substantial miscorrelation between ringback at the edge finger versus the core. The miscorrelation creates instances where a signal fails to satisfy ringback requirements at the edge finger, but passes the ringback specification at the core. For this reason, signal integrity is specified at the core. Ringback guidelines are supplied at the edge finger, as shown in Table 2-6. Any measurement at the edge finger that violates the guidelines should be simulated to verify that it meets the specification at the core.

Table 2-6. Ringback Guidelines at the Intel® Pentium® II Processor Edge Fingers

Edge	Guideline @ Processor Edge	Spec @ Processor Core
	Finger
Rising	1.29V	1.12V1
Falling	0.71V	0.88V

NOTE:

1.Ringback specifications follow the methodology described in Intel®Pentium® II Processor at 233 MHz, 266 MHz, 300 MHz and 333 MHz Datasheet.

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