Debug Recommendations

The Global Descriptor Table (GDT) must be aligned. The GDT must be located on a DWord boundary, or else setting the PE bit and branching will cause a SHUTDOWN transaction.

The ITP “pins” command may be used to check reset configuration pin states. Be aware, however, that observing pin state during reset will not reveal anything about the stability or timing of the configuration signals around the reset edge.

You can expect the following processor system bus activity after reset: BNR# stops toggling approximately 2.8 million BCLKs after the deassertion of RESET#, if BIST is not configured to run. If BIST is configured to run, BNR# will continue to toggle until BIST completion.

After BNR# stops toggling, the PICD[1:0]# signals begin the MP initialization to determine

the bootstrap processor. In a single processor boot, two 21-cycle short messages are transmitted on the APIC. (Refer to the Intel® Pentium® Pro Family Developer’s Manual, Vol. III). The following fields are expected and all others are “don’t care.” Note that PICD[1:0]# are active low so the pin electrical levels will be the complement of the numbers presented here.

Interrupt Vector = 0x4N for the first cycle and 0x1N for the second cycle. Where “N” is the processor number

DM = 0, D3-D0 = 1111 (all including self shorthand)

Trigger Mode = 1 (edge)

Level = 0 (deasserted)

Delivery Mode = 000 (fixed)

Intel®440GX AGPset Design Guide

4-6

Page 106
Image 106
Intel 440GX manual Debug Recommendations

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.