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Intel General Design Recommendations, Transitioning from Intel 440BX AGPset to Intel 440GX

Models: 440GX

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Introduction

1.4.2General Design Recommendations

1.Intel recommends using an industry standard programmable Voltage Regulator Module

(VRM) installed in a VRM header or an onboard programmable voltage regulator designed for Intel® Pentium® II processors.

2.Systems should be capable of varying the system bus to processor core frequency ratio per the System Bus to Core Frequency Multiplier Configuration table of the Intel® Pentium® II processor datasheet. The Intel® Pentium® II processor uses the following signals to configure the internal clock multiplier ratio: LINT[0]/INTR, IGNNE#, A20M#, LINT[1]/NMI. Follow the recommendations in this document to ensure that adequate hold times are met on the

strapping signals. Ensure the output of the strapping logic is a Vcc2.5 logic level for connection to the Slot 1 connector. This can be accomplished using an open-drain output driver with pull- ups to Vcc2.5.

3.Please prepare for additional thermal margin for increases of 1-5W for higher performance or otherwise enhanced processor.

4.Motherboard designs targeted for system integrators should design to the Boxed Intel® Pentium® II processor electrical, mechanical and thermal specifications provided in the Intel® Pentium® II processor datasheet, most notably the required fan power header, fan/heatsink physical clearance on the motherboard.

5.Motherboard designs should incorporate a retention mechanism, retention mechanism attach mount and heatsink support mounting holes and keep out areas for the Intel® Pentium® II processor and boxed Intel® Pentium® II processor.

1.4.3Transitioning from Intel® 440BX AGPset to Intel® 440GX

AGPset Design

1.The 82443GX supports 2GB using 128M or 256M memory technology. The design guidelines for MAA14 and MAB14 are the same as MAA-13 and MAB-13 on the 82443BX.

2.Intel® 440GX AGPset supports 100 MHz system bus and 100 MHz SDRAM Memory only.

3.There is no 3 DIMM support with the Intel 440GX AGPset.

Intel®440GX AGPset Design Guide

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Intel General Design Recommendations, Transitioning from Intel 440BX AGPset to Intel 440GX, AGPset Design, Introduction

Contents

Design Guide Intel 440GX AGPsetMarch Intel440GX AGPset Design Guide Contents Validation 82371EB PIIX4E 4.3.1 IntelPentiumII Processor LAI Issue Figures Tables Intel440GX AGPset Design Guide Revision HistoryDate RevisionIntel440GX AGPset Design Guide Introduction Page Introduction 1.1 About This Design GuideIntroduction Intel 440GX AGPset Datasheet WWW order number 1.2 ReferencesIntroduction AP-589 EMI WWW order number1.3 Intel Pentium II Processor / Intel 440GX AGPset Overview 1.3.1 Intel Pentium II ProcessorIntroduction Introduction 1.3.2 Intel 440GX AGPset1.3.2.2 DRAM Interface 1.3.2.1 System Bus Interface1.3.2.3 Accelerated Graphics Port Interface Introduction1.3.3 PCI-to-ISA/IDE Xcelerator PIIX4E 1.3.4 Wired for Management Initiative1.3.2.4 PCI Interface 1.3.2.5 System Clocking1.3.3.2 Remote Service Boot 1.3.3.1 InstrumentationIntroduction 1.4 Design Recommendations 1.3.3.4 Power Management1.4.1 Voltage Definitions 1.3.3.3 Remote Wake-Up1.4.3 Transitioning from Intel 440BX AGPset to Intel 440GX 1.4.2 General Design RecommendationsAGPset Design IntroductionIntel440GX AGPset Design Guide IntroductionMotherboard Design Page Motherboard Layout and Routing Figure 2-1. Major Signal Sections 82443GX Top ViewGuidelines 2.1 BGA Quadrant AssignmentATX Form Factor Motherboard Layout and Routing Guidelines2.2 Board Description Motherboard Layout and Routing GuidelinesNLX Form Factor Motherboard Layout and Routing Guidelines Figure 2-4. Four Layer Board Stack-upMotherboard Layout and Routing Guidelines 2.3 Routing Guidelines2.3.2 GTL+ Layout Recommendations 2.3.1 GTL+ Description2.3.3 Single Processor Design 2.3.3.1 Single Processor Network Topology and Conditions2.3.3.2 Single Processor Recommended Trace Lengths Table 2-1. Recommended Trace Lengths for Single Processor DesignMotherboard Layout and Routing Guidelines 2.3.5 Single Processor Systems-Single-End Termination SET 2.3.4 Dual Processor Systems2.3.4.1 Dual Processor Network Topology and Conditions 2.3.4.2 Dual Processor Recommended Trace Lengths2.3.5.2 SET Trace Length Requirements Table 2-3. SET Trace Length RequirementsMotherboard Layout and Routing Guidelines 2.3.6.1 Minimizing Crosstalk 2.3.6 Additional Guidelines2.3.6.2 Practical Considerations Motherboard Layout and Routing GuidelinesMotherboard Layout and Routing Guidelines 2.3.7 Design Methodology2.3.8 Performance Requirements Figure 2-12. GTL+ Design ProcessMotherboard Layout and Routing Guidelines 2.3.10 Pre-Layout Simulation Sensitivity Analysis 2.3.9 Topology Definition2.3.11 Simulation Methodology Table 2-4. Recommended 100 MHz System Flight Time Specs2.5 Post-Layout Simulation 2.4 Placement & LayoutFigure 2-13. Pre-layout simulation process Motherboard Layout and Routing Guidelines2.6 Validation 2.5.1 Crosstalk and the Multi-Bit Adjustment Factor2.6.1 Flight Time Measurement Motherboard Layout and Routing GuidelinesMotherboard Layout and Routing Guidelines 2.6.2 Signal Quality MeasurementEdge Guideline @ Processor Edge2.7 Timing Analysis Motherboard Layout and Routing GuidelinesThe terms used in the equations are described in Table Table 2-11. Recommended 100 MHz System Flight Time Specs Table 2-10. Recommended 100 MHz System Timing ParametersMotherboard Layout and Routing Guidelines Tflight,minFigure 2-14. AGP Connector Layout Guidelines 2.8.1 AGP Connector “Up Option Layout Guidelines2.8 AGP Layout and Routing Guidelines Table 2-12. Data and Associated Strobe2.8.2 On-board AGP Compliant Device “Down” Option Layout Guidelines Table 2-14. Control Signal Line Length RecommendationsTable 2-13. Source Synchronous Motherboard Recommendations Motherboard Layout and Routing GuidelinesFigure 2-15. On-board AGP Compliant Device Layout Guidelines Table 2-16. Control Signal Line Length RecommendationsTable 2-15. Source Synchronous Motherboard Recommendations Motherboard Layout and Routing Guidelines2.9 82443GX Memory Subsystem Layout and Routing Guidelines Figure 2-16. FET Switch Example2.9.1 100 MHz 82443GX Memory Array Considerations Motherboard Layout and Routing Guidelines2.9.1.2 Adding Additional Decoupling Capacitor 2.9.1.1 Matching the Reference PlanesFigure 2-17. Registered SDRAM DIMM Example Table 2-17. MDx lines Reference Planes Routing2.9.1.3 Trace Width vs. Trace Spacing 2.9.2 Memory Layout & Routing GuidelinesFigure 2-19. 4 DIMMs Single or Double-Sided Motherboard Layout and Routing GuidelinesFigure 2-20. Motherboard Model-Data MDxx, 4 DIMMs Table 2-18. FET Switch DQ Route Example82443GX Motherboard Layout and Routing GuidelinesFigure 2-22. Motherboard Model-DQMA1,5, 4 DIMMs Figure 2-21. Motherboard Model-DQMA0,24,67, 4 DIMMsFigure 2-23. Motherboard Model-DQMA1,5, 4 DIMMs Motherboard Layout and Routing GuidelinesFigure 2-25. Motherboard Model-CSA#/CSB#, 4 DIMMs Figure 2-24. Motherboard Model-DQMB1,5, 4 DIMMsFigure 2-26. Motherboard Model-SRASA#, 4 DIMMs Motherboard Layout and Routing GuidelinesTable 2-20. Motherboard Model SCASA#, 4 DIMMs Table 2-19. Motherboard Model SRASB#, 4 DIMMsTable 2-21. Motherboard Model SCASB#, 4 DIMMs Motherboard Layout and Routing GuidelinesTable 2-23. Motherboard Model WEB#, 4 DIMMs Table 2-22. Motherboard Model WEA#, 4 DIMMsTable 2-24. Motherboard Model MAA140, 4 DIMMs Motherboard Layout and Routing Guidelines2.9.4 PCI Bus Routing Guidelines 2.9.3 4 DIMM Routing Guidelines NO FETTable 2-25. Motherboard Model MAB12,11,90#, MAB14,13,10, 4 DIMMs Figure 2-27. Motherboard Model-Data MDxx Lines, 4 DIMMs No FETHost Bridge Controller 492 BGA 2.9.5 Decoupling Guidelines Intel 440GX AGPset PlatformFigure 2-28. PCI Bus Layout Example Figure 2-29. 82443GX Decoupling2.9.6.1 Clock Routing Spacing 2.9.6 Intel 440GX AGPset Clock Layout Recommendations2.9.6.2 System Bus Clock Layout Figure 2-30. Clock Trace Spacing Guidelines2.9.6.3 PCI Clock Layout 2.9.6.4 SDRAM Clock LayoutMotherboard Layout and Routing Guidelines 2.9.6.5 AGP Clock Layout Figure 2-31. AGP Clock LayoutMotherboard Layout and Routing Guidelines Design Checklist Page Design Checklist Design Checklist3.1 Overview 3.2 Pull-up and Pull-down Resistor Values3.3.1 Intel Pentium II Processor 3.3 Intel Pentium II Processor ChecklistFigure 3-1. Pull-up Resistor Example Table 3-1. Slot Connectivity Sheet 1 ofTable 3-1. Slot Connectivity Sheet 2 of Design ChecklistIntel440GX AGPset Design Guide Table 3-1. Slot Connectivity Sheet 3 of Table 3-2. GND & Power Pin DefinitionDesign Checklist Intel440GX AGPset Design Guide3.3.3 Intel Pentium II Processor Signals 3.3.2 Intel Pentium II Processor ClocksDesign Checklist DBRESET ITP Reset signal requires a 240 ohm pull-up to VCC3 Design Checklist3.3.5 Dual-Processor DP Slot 1 Checklist 3.3.4 Uni-Processor UP Slot 1 Checklist3.3.6 Slot 1 Decoupling Capacitors 3.3.7 Voltage Regulator Module, VRM3.4.1 CK100 - 100 MHz Clock Synthesizer 3.4 Intel 440GX AGPset ClocksTable 3-3. Processor Frequency Select Design Checklist3.4.3 GCKE and DCLKWR Connection 3.4.2 CKBF - SDRAM 1 to 18 Clock BufferFigure 3-2. GCKE & DCLKWR Connections Design Checklist3.5.1 82443GX Interface 3.5 82443GX Host BridgeTable 3-4. 82443GX Connectivity Sheet 1 of Design ChecklistDesign Checklist Table 3-4. 82443GX Connectivity Sheet 2 ofIntel440GX AGPset Design Guide 3-113.5.3 82443GX PCI Interface 3.5.2 82443GX GTL+ Bus InterfaceTable 3-4. 82443GX Connectivity Sheet 3 of Design Checklist3.5.4 82443GX AGP Interface Table 3-5. Strapping OptionsDesign Checklist 3.6.1 SDRAM Connections 3.6 Intel 440GX AGPset Memory InterfaceTable 3-6. SDRAM Connectivity Design ChecklistFigure 3-3. Current Solution With Existing FET Switches 3.6.2 DIMM Solution With FET Switches3.6.3 Registered SDRAM Design Checklist3.7.1 PIIX4E Connections 3.7 82371EB PIIX4ETable 3-7. PIIX4E Connectivity Sheet 1 of Design ChecklistDesign Checklist Table 3-7. PIIX4E Connectivity Sheet 2 ofIntel440GX AGPset Design Guide 3-17Design Checklist Table 3-7. PIIX4E Connectivity Sheet 3 ofIntel440GX AGPset Design Guide 3-18Design Checklist Table 3-7. PIIX4E Connectivity Sheet 4 ofIntel440GX AGPset Design Guide 3-193.7.2.1 Cabling 3.7.2 IDE Routing Guidelines3.7.2.2 Motherboard Table 3-8. IDE Series TerminationFigure 3-4. Series Resistor Placement for Primary IDE Connectors PIIX4EDesign Checklist 3.7.3 PIIX4E Power And Ground Pins 3.8 PCI Bus SignalsTable 3-9. PIIX4E PWR & GND Design Checklist3.10 ISA and X-Bus Signals ISA SignalsTable 3-10. Non-PIIX4E PCI Signals Table 3-11. Non-PIIX4E ISA Signals3.12 IDE Interface 3.11 USB InterfaceTable 3-12. Non-PIIX4E IDE Design Checklist3.13.1 Dual-Footprint Flash Design 3.13 Flash Design3.13.2 Flash Design Considerations Figure 3-5. Dual Footprint Flash Layouts1Mbit/2Mbit XD70Flash Figure 3-6. nterfacing Intel’s Flash with PIIX4E in DesktopTable 3-13. Flash Vpp Recommendations Design ChecklistWrite Protection 3.15 Power Management Signals 3.14 System and Test SignalsFigure 3-7. Interfacing Intel’s Flash with PIIX4E in Desktop Design ChecklistA S L O T O C C B S L O T O C C4.7K V R M 1 P W R G D Simplified P W R G O O D a n d P W R O K generation logic VCC3V R M 2 P W R G D I T P R E S E T A T X P S P O K Note The polarities have been altered to simplify drawingDesign Checklist 3.15.1 Power Button ImplementationDesign Checklist 3.16 MiscellaneousDesign Checklist 3.17 82093AA IOAPIC3.18 Manageability Devices 3.18.1 Max1617 Temperature Sensor3.18.2 LM79 Microprocessor System Hardware Monitor Design ChecklistDesign Checklist 3.18.3 82558B LOM Checklist3.19.1 USB and Multi-processor BIOS 3.19 Software/BIOS3.18.4 Wake On LAN WOL Header Design Checklist3.21 Mechanicals 3.20 Thermals / Cooling Solutions3.19.2 Design Considerations 3.20.1 Design Considerations3.21.1 Design Considerations 3.22 Electricals3.22.1 Design Considerations Design Checklist3.24 Applications and Add-in Hardware 3.23 Layout Checklist3.23.1 Routing and Board Fabrication 3.23.2 Design ConsiderationDebug Recommendations Page 4.1 Slot 1 Test Tools Debug Recommendations4.2 Debug/Simulation Tools 4.2.1 Logic Analyzer Interface LAI4.3.1 Intel Pentium II Processor LAI Issue 4.3 Debug Features4.2.3 Bus Functional Model BFM 4.2.4 I/O Buffer ModelsDebug Recommendations Figure 4-1. LAI Probe Input CircuitDebug Recommendations 4.3.2 Debug Logic Recommendations4.3.3 Debug Layout 4.3.4 Debug Procedures4.3.2.1 Debug Considerations 4.3.3.1 Design ConsiderationsDM = 0, D3-D0 = 1111 all including self shorthand Debug RecommendationsThird Party Vendors Page Third-Party Vendor Information Table 5-1. Slot 1 ConnectorProcessors Third-Party Vendor Information5.1.2 Voltage Regulator Control Silicon 5.1.1 Voltage Regulator ModulesTable 5-4. Voltage Regulator Modules Table 5-5. Voltage Regulator Control Silicon Vendors5.2.3 FET Switches4 DIMM/FET Design 5.2.2 Power Management ComponentsTable 5-7. Power Management Component Vendors Table 5-8. FET Switch Vendors5.3 Other Processor Components 5.3.1 Slot 1 Connector5.3.2 Mechanical Support 5.3.3 Heat sinksReference Design Schematics Page Design Intel 440GX AGPset Platform ReferenceIntel440GX AGPset Platform Reference Design 4 andThe GCKE shift register circuit is also shown Intel440GX AGPset Platform Reference DesignUltra I/O Component Intel440GX AGPset Platform Reference DesignIntel440GX AGPset Platform Reference Design Power Connectors Front Panel JumpersPull-up and Pull-down Resistors 34-35