Intel manual Intel440GX AGPset Platform Reference Design

Intel®440GX AGPset Platform Reference Design

82443GX Component (System bus and DRAM Interfaces) 8

This page shows the 82443GX component, System bus and DRAM Interfaces. The 82443GX connects to the lower 32 bits of the CPU address bus and the CPU control signals, and generates DRAM control signals for the memory interface. In this design, the 82443GX is configured to interface to a memory array of 4 DIMMs for a DP design.

The CKBF is also shown on this page. The 82443GX delivers a single SDRAM clock to the CKBF which is a 18 output buffer, with an I2C interface which may be used to disable unused clock outputs for EMI reduction. It outputs 4 clocks to each DIMM socket, and 1 back to the 82443GX for data timings. The last clock is used for the Global Clock Enable (GCKE) logic.

82443GX Component (PCI and AGP Interfaces) 9

This page shows the 82443GX component, PCI and AGP Interfaces. The definition of pin AF3 has been changed from SUSCLK to GX-PWROK. Like PIIX4E PWROK, it is connected to the PWROK logic from the Power Connector page (Page 32). Note the GCLKIN and GCLKOUT trace length requirements on the AGP interface.

82443GX Component (Memory and System Data Bus Interfaces) 10

This page shows the 82443GX component, Memory and System Data Bus Interfaces. GTL_REF signal are also shown on this page. Ideally, the GTL_REF signals should be decoupled separately, and as close as possible to the 82443GX component, but this is not a requirement.

The GCKE shift register circuit is also shown.

FET Switch Component 11 and 12

These FET switches are used for a 4 DIMM memory configuration. 500 ohm series resistors have been added to all of the grounded xA2 input pins.

DIMM Connectors 0, 1, 2 and 3 for the DP 4-DIMM schematics 13-16

These three pages show the DRAM interface connections from the 82443GX to the DRAM array.

The serial presence detect pins are addressed as 1010-000,001,011 respectively. 82443GX strap pull-up/pull-downs will be located on selected MAB# lines. REGE (pin 147) on each DIMM socket should be pulled high to enable registered DIMMs,

PIIX4E Component 17

This page shows the PIIX4E component. The PIIX4E component connects to the PCI bus, dual IDE connectors, and the ISA bus. This reference design supports a subset of the power management features of the PIIX4E.

PIIX4E Component 18

This page shows the PIIX4E component Interrupts, USB, DMA, power management, X-Bus, and GPIO interfaces. Also shown is the CLOCKRUN# pull-down and the external logic needed to handle a power loss condition.

IOAPIC Component 19

This sheet shows the connection for the IOAPIC controller to the various PIIX4E and processor interrupts.

A-2 Intel®440GX AGPset Design Guide