Design Checklist

3.6Intel® 440GX AGPset Memory Interface

3.6.1SDRAM Connections

Table 3-6. SDRAM Connectivity

82443GX Pins/Connection

DIMM Pins

Pin Function

 

 

 

CKBF buffer outputs DCLK[x:y]

CK[3:0] (4 DCLKs per DIMM)

Clock

 

 

 

CS_A[7:0]#

S#[1:0] (2 CS per DIMM)

Chip Select

 

 

 

CS_B[7:0]#

S#[3:2] (2 CS per DIMM)

Chip Select

 

 

 

GND

A13

Address

 

 

 

MAx[9:0]#, MAx10

A[10:0]

Address

 

 

 

MAx11#

BA0

Address

 

 

 

Max12#

BA1

Address

 

 

 

MAA13#, MAB13

A11

Address

 

 

 

MAA14, MAB14

A12

Address

 

 

 

MDx[63:0] (from FET)

DQ[63:0]

Data

MD[63:0] (NO FET)

 

 

 

 

 

MECC[7:0]

CB[7:0]

Error Checking and Correction

 

 

 

Strap for SMBus individual

SA[2:0]

SMBus Address

Address

 

 

 

 

 

SMBDATA

SDA

SMBus Data

 

 

 

SMBCLK

SCL

SMBus Clock

 

 

 

SCASx#

CAS#

SDRAM Column Address Select

 

 

 

SRASx#

RAS#

SDRAM Row Address Select

 

 

 

WEx#

WE0#

Write Enable

 

 

 

NOTES:

1.Some of the pin ranges above are dependent on which DIMM is being reviewed. “x” and “y” indicate signal copies.

2.MAAxx address lines need to be routed to the two DIMM sockets closest to the 82443GX. MABxx# will be routed to the one or two DIMM sockets furthest from the 82443GX. Selected MABxx# lines will also require strapping options to properly configure the 82443GX.

3.Can either be a FET or no-FET solution. A FET solution will require the use of six 56-pin FET switch multiplexers. The most common FET switches available are of the 5V family. A no-FET solution must adhere to the strict no-FET design layout guidelines.

4.The MD, MECC and the DQM lines require “T” routing for load balancing.

5.Copies of SRAS#, SCAS#, WE# should be evenly distributed throughout the memory array.

6.MABxx# pins (except for MAB10, MAB13, and MAB14) are inverted for signal integrity reasons. MAB10, MAB13, and MAB14 are not inverted to maintain correct SDRAM commands.

7.Series termination resistors are not required on the motherboard for DIMM signals (MD, MA, DQM, CS, etc.).

8.See the SDRAM Serial Presence Detect Data Structure specification for information on the EEPROM register contents.

9.The PC SDRAM Unbuffered DIMM Specification, Rev 1.0, dated Feb 1998, shows pin 81 of the DIMM module is the WP (write protect) pin for the SPD EEPROM. The block diagrams show there is a 47K pull- down resistor tied to the WP pin. This allows the DIMM manufacturers to write SPD data to the EEPROM. An OEM may wish to use the SPD EEPROM to write information into the DIMMs at production for system level checkout to identify the DIMM installed as being shipped with the system. For this reason, the OEM may wish to include some logic to control the level on pin 81 of the DIMM modules so that after the DIMM is tagged, they can be write protected again. If this pin is pulled high on the motherboard, the DIMM SPD EEPROM is write protected. Pin 81 of the DIMM sockets on the 82443GX dual processor reference schematics currently shows a “NC”, no connects. If an OEM wishes to write protect the SDRAM SPD EEPROMS, then these pins should be pulled high.

Intel®440GX AGPset Design Guide

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Intel manual Intel 440GX AGPset Memory Interface, Sdram Connections, Sdram Connectivity

440GX specifications

The Intel 440GX chipset was launched in 1997 as part of Intel's series of chipsets known as the 440 family, and it served as a critical component for various Pentium II and Pentium III-based motherboard architectures. Specifically designed for the second generation of Intel’s processors, the 440GX delivered enhanced performance and supported a range of important technologies that defined PC architectures of its time.

One of the main features of the Intel 440GX was its support for a 100 MHz front-side bus (FSB), which significantly improved data transfer rates between the CPU and the memory subsystem. This advancement allowed the 440GX to accommodate both the original Pentium II processors as well as the later Pentium III chips, providing compatibility and flexibility for system builders and consumers alike.

The 440GX chipset included an integrated AGP (Accelerated Graphics Port) controller, which supported AGP 2x speeds. This enabled high-performance graphics cards to be utilized effectively, delivering many enhanced graphics capabilities for gaming and multimedia applications. The AGP interface was crucial at the time as it offered a dedicated pathway for graphics data, increasing bandwidth compared to traditional PCI slots.

In terms of memory support, the 440GX could address up to 512 MB of SDRAM, allowing systems built with this chipset to run comfortably with sufficient memory for the era’s demanding applications. The memory controller was capable of supporting both single and double-sided DIMMs, which provided versatility in memory configuration for system builders.

Another notable feature of the Intel 440GX was its support for multi-processor configurations through its Dual Processors support feature. This allowed enterprise and workstation computers to leverage the performance advantages of multiple CPUs, making the chipset suitable for business and professional environments where multitasking and high-performance computing were essential.

On the connectivity front, the chipset supported up to six PCI slots, enhancing peripheral device integration and expansion capabilities. It also included integrated IDE controllers, facilitating connections for hard drives and CD-ROM devices.

Overall, the Intel 440GX chipset represented a balanced combination of performance, flexibility, and technology advancements for its time. Its introduction helped establish a foundation for subsequent advancements in PC technology and set the stage for more powerful computing systems in the years to come.